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    FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS
    3.
    发明申请
    FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS 有权
    在源/排水管线和通道之间具有绝缘衬套的闪存

    公开(公告)号：US20090213656A1

    公开(公告)日：2009-08-27

    申请号：US12038612

    申请日：2008-02-27

    申请人： Shaw Hung Ku ,  Teng Hao Yeh ,  Shih-Chin Lee ,  Shang-Wei Lin ,  Chia-Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

    发明人： Shaw Hung Ku ,  Teng Hao Yeh ,  Shih-Chin Lee ,  Shang-Wei Lin ,  Chia-Wei Wu ,  Tzung Ting Han ,  Ming Shang Chen ,  Wenpin Lu

    IPC分类号： G11C11/34 ,  H01L21/8247

    CPC分类号： H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

    摘要翻译： 存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。 沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。 绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。 多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。 电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。 电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。 制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

    TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS
    4.
    发明申请
    TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS 有权
    使用模拟编程操作的充电跟踪存储器的工具

    公开(公告)号：US20090276737A1

    公开(公告)日：2009-11-05

    申请号：US12182352

    申请日：2008-07-30

    申请人： Shaw Hung Ku ,  Chia-Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

    发明人： Shaw Hung Ku ,  Chia-Wei Wu ,  Ming Shang Chen ,  Wenpin Lu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/78

    摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

    摘要翻译： 一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流 电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。 可以对包括电荷捕获结构的晶体管计算阈值电压的变化。 参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。

    Structure of probe
    5.
    发明授权
    Structure of probe 有权
    探头结构

    公开(公告)号：US07898274B2

    公开(公告)日：2011-03-01

    申请号：US11745463

    申请日：2007-05-08

    申请人： Chia-Wei Wu

    发明人： Chia-Wei Wu

    IPC分类号： G01R31/20

    CPC分类号： G01R1/06772 ,  G01R1/06727 ,  G01R1/06733

    摘要： A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test.

    摘要翻译： 分离式探头用于与待测物体接触以检测其电气特性。 本发明提供的探针具有用于与待测物体接触的接触头，以及第一针体和第二针体。 第一针体连接到接触头，以将测试信号传送到被测物体进行检测。 此外，第二针体还连接到接触头，以通过测试信号传输由被测物体产生的响应信号，以获得被测物体的电特性。

    Method for manufacturing memory cell
    6.
    发明授权
    Method for manufacturing memory cell 有权
    制造存储单元的方法

    公开(公告)号：US07795088B2

    公开(公告)日：2010-09-14

    申请号：US11753850

    申请日：2007-05-25

    申请人： Tzu-Hsuan Hsu ,  Ming-Hsiang Hsueh ,  Yen-Hao Shih ,  Chia-Wei Wu

    发明人： Tzu-Hsuan Hsu ,  Ming-Hsiang Hsueh ,  Yen-Hao Shih ,  Chia-Wei Wu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28282 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

    摘要： A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer. Subsequently, a gate is formed on the substrate and straddles the protection layer, the charge trapping structures and the fin structure. Afterward, source/drain regions are formed in the fin-structure exposed by both sides of the gate.

    摘要翻译： 提供一种用于制造存储器单元的方法。 首先，提供衬底，其中衬底层和材料层已经顺序形成在衬底上。 此后，在衬底上形成图案化掩模层。 然后，修整图案化的掩模层。 随后，通过使用图案化掩模层作为掩模来去除材料层的一部分，衬垫层的一部分和衬底的一部分，以在衬底中限定多个鳍结构。 之后，去除图案化的掩模层，并且形成翅片结构中的多个隔离结构。 隔离结构的表面比翅片结构的表面低。 之后，在基片上形成电荷俘获结构，覆盖翅片结构。 成功地，去除一部分电荷捕获结构以暴露材料层。 然后，处理过程将材料层转变成保护层。 随后，在基板上形成栅极，跨越保护层，电荷捕获结构和鳍结构。 之后，源极/漏极区域形成在由栅极两侧暴露的鳍状结构中。

    Method for forming shallow trench isolation with rounded corners by using a clean process
    9.
    发明申请
    Method for forming shallow trench isolation with rounded corners by using a clean process 审中-公开
    通过使用清洁工艺形成具有圆角的浅沟槽隔离的方法

    公开(公告)号：US20060148197A1

    公开(公告)日：2006-07-06

    申请号：US11134372

    申请日：2005-05-23

    申请人： Chia-Wei Wu ,  Cheng-Shun Chen ,  Jung-Yu Hsieh ,  Ling Yang

    发明人： Chia-Wei Wu ,  Cheng-Shun Chen ,  Jung-Yu Hsieh ,  Ling Yang

    IPC分类号： H01L21/76 ,  H01L21/302

    CPC分类号： H01L21/30608 ,  H01L21/76232

    摘要： In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a trench, a liner oxide is formed over the trench, an STI insulator is formed in the trench, and the hard mask and the pad oxide are removed. Before the formation of the liner oxide, a clean process is performed that comprises applying silicon-consuming solution to round the top corners of the trench.

    摘要翻译： 在用于在衬底上具有衬垫氧化物的硅衬底中形成STI的方法中，在衬垫氧化物上方形成硬掩模，对硬掩模和衬垫氧化物进行构图以形成开口，通过开口蚀刻硅衬底 为了形成沟槽，在沟槽上形成衬垫氧化物，在沟槽中形成STI绝缘体，并且去除硬掩模和衬垫氧化物。 在形成衬垫氧化物之前，执行清洁工艺，其包括将消耗硅消耗溶液施加到沟槽的顶角四周。

    Vertical channel transistor structure and manufacturing method thereof
    10.
    发明授权
    Vertical channel transistor structure and manufacturing method thereof 有权
    垂直沟道晶体管结构及其制造方法

    公开(公告)号：US09246015B2

    公开(公告)日：2016-01-26

    申请号：US12892044

    申请日：2010-09-28

    申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

    发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

    IPC分类号： H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L27/12

    CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

    摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

    摘要翻译： 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。