公开(公告)号：US20150002243A1

公开(公告)日：2015-01-01

申请号：US14487821

申请日：2014-09-16

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H01P5/12

CPC classification number: H01P1/182 ,  H01P1/184 ,  H01P9/00 ,  H03F3/189 ,  H03F3/211 ,  H03F3/602 ,  H03F3/68 ,  H03H7/185 ,  H03H7/422

Abstract: Power-dividing and/or power-combining circuits have inputs, outputs, and at least three electrical pathways, with substantially equal input and output reflection coefficients. An electronic device may be provided in each of the pathways. Additionally, isolation circuits or devices can be inserted between signal lines to provide isolation between inputs, in the case of combining, or outputs, in the case of dividing. In one embodiment, multiple phase shift components are electrically connected to electronic devices in the electrical pathways. These phase shift components are selected so that a vector sum of the reflected signals from the inputs in combining and/or to the outputs in dividing is substantially minimized.

Abstract translation: 功率分配和/或功率合并电路具有基本上相等的输入和输出反射系数的输入，输出和至少三个电路径。 可以在每个路径中提供电子设备。 此外，隔离电路或器件可以插入信号线之间，以在组合的情况下提供输入之间的隔离，或者在分割的情况下输出。 在一个实施例中，多个相移元件电连接到电路中的电子器件。 选择这些相移分量，使得来自组合中的输入和/或分割中的输出的反射信号的向量和基本上最小化。

公开(公告)号：US20170346151A1

公开(公告)日：2017-11-30

申请号：US15428623

申请日：2017-02-09

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H01P5/16

CPC classification number: H01P5/16 ,  H03H7/00

Abstract: A power combiner and divider device includes a first port electrically connected to a first impedance line and a second impedance line; a second port electrically connected to the first impedance line and a coupled line; a third port electrically connected to the second impedance line and the coupled line; a third impedance line electrically connected to the coupled line; and a fourth impedance line electrically connected to each of the third impedance line and the coupled line.

公开(公告)号：US10079420B2

公开(公告)日：2018-09-18

申请号：US15428623

申请日：2017-02-09

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H01P5/12 ,  H01P5/16 ,  H03H7/00

CPC classification number: H01P5/16 ,  H03H7/00

Abstract: A power combiner and divider device includes a first port electrically connected to a first impedance line and a second impedance line; a second port electrically connected to the first impedance line and a coupled line; a third port electrically connected to the second impedance line and the coupled line; a third impedance line electrically connected to the coupled line; and a fourth impedance line electrically connected to each of the third impedance line and the coupled line.

公开(公告)号：US20170171012A1

公开(公告)日：2017-06-15

申请号：US15422219

申请日：2017-02-01

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H04L27/34 ,  H04B1/04

CPC classification number: H04L27/3405 ,  H03C5/00 ,  H04B1/0483

Abstract: A radio transmitter having a RF signal source. A splitter receives an input signal from the signal source and divides that input signal into two output signals. Alternatively, two signal generators provide the two output signals. These output signals are fed into two phase shifters. A phase control signal is applied to each phase shifter so that the vector sum of the output signals represents the desired amplitude and phase of the desired transmitted signal. The outputs of both phase shifters are both frequency multiplied and amplified before recombining to form the transmitter output signal. Moreover, the outputs can be transmitted separately and combined at the receiver. Alternatively, in the case of two signal sources, the signal paths may be at different transmitter locations.

公开(公告)号：US09000865B2

公开(公告)日：2015-04-07

申请号：US13922980

申请日：2013-06-20

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H01P5/12 ,  H03F3/68

CPC classification number: H03F3/68 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F2203/21106

Abstract: Power-dividing and/or power-combining circuits have inputs, outputs, at least three electrical pathways, and at least three electronic devices, such as amplifiers, with substantially equal input and output reflection At least one of the electronic devices is in each of the electrical pathways. In one embodiment, multiple phase shift components, such as delay lines, are electrically connected to the electronic devices in each of the electrical pathways. These phase shift components are selected so that a vector sum of the reflected signals from the electronic devices to the inputs and/or the outputs is substantially minimized. In another embodiment, a serial bus extends from the inputs/outputs and at least three pathways in the circuit. The serial bus includes serially-connected impedance-providing components positioned among at least three pathways with the impedance-providing components increasing in impedance from one end to the other end of the serial bus in an amount sufficient to produce a substantially equal amount of power to each of the electronic devices and to substantially minimize input and output reflections.

Abstract translation: 功率分配和/或功率组合电路具有输入，输出，至少三个电路径，以及至少三个具有基本上相等的输入和输出反射的电子装置，例如放大器。至少一个电子装置在 电路。 在一个实施例中，诸如延迟线的多个相移分量电连接到每个电路径中的电子设备。 选择这些相移分量，使得从电子设备到输入和/或输出的反射信号的矢量和基本上最小化。 在另一个实施例中，串行总线从电路中的输入/输出和至少三个通路延伸。 串行总线包括位于至少三个通路之间的串联连接的阻抗提供组件，其中阻抗提供部件的阻抗从串行总线的一端增加到另一端，其量足以产生基本相等的功率 每个电子设备并且基本上最小化输入和输出反射。

公开(公告)号：US20140175514A1

公开(公告)日：2014-06-26

申请号：US13724598

申请日：2012-12-21

Applicant: U.S. ARMY RESEARCH LABORATORY ATTN: RDRL-LOC-I

Inventor： Ali Darwish ,  Hingloi Alfred Hung

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/7786 ,  H01L29/812

Abstract: A ring-shaped transistor includes a set of gates. Each gate of the set is disposed between a corresponding source and a corresponding drain. The set of gates are arranged such that all of the set of gates cannot be aligned with fewer than three imaginary straight lines drawn through the gates, with one of the imaginary straight lines passing only once though each of the set of gates.

Abstract translation: 环形晶体管包括一组门。 该组的每个栅极设置在相应的源极和相应的漏极之间。 所述一组栅极被布置成使得所述一组栅极不能与通过栅极绘制的少于三条假想直线对准，其中一条假想直线仅通过该组栅极中的每一条。

公开(公告)号：US10069669B2

公开(公告)日：2018-09-04

申请号：US15422219

申请日：2017-02-01

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M Darwish ,  Hingloi Alfred Hung

IPC: H04L27/36 ,  H04L27/34 ,  H04B1/04

Abstract: A radio transmitter having a RF signal source. A splitter receives an input signal from the signal source and divides that input signal into two output signals. Alternatively, two signal generators provide the two output signals. These output signals are fed into two phase shifters. A phase control signal is applied to each phase shifter so that the vector sum of the output signals represents the desired amplitude and phase of the desired transmitted signal. The outputs of both phase shifters are both frequency multiplied and amplified before recombining to form the transmitter output signal. Moreover, the outputs can be transmitted separately and combined at the receiver. Alternatively, in the case of two signal sources, the signal paths may be at different transmitter locations.

公开(公告)号：US09362602B2

公开(公告)日：2016-06-07

申请号：US14487821

申请日：2014-09-16

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H01P5/12 ,  H03F3/68 ,  H01P1/18 ,  H01P9/00 ,  H03H7/42 ,  H03H7/18 ,  H03F3/189 ,  H03F3/21 ,  H03F3/60

CPC classification number: H01P1/182 ,  H01P1/184 ,  H01P9/00 ,  H03F3/189 ,  H03F3/211 ,  H03F3/602 ,  H03F3/68 ,  H03H7/185 ,  H03H7/422

Abstract: Power-dividing and/or power-combining circuits have inputs, outputs, and at least three electrical pathways, with substantially equal input and output reflection coefficients. An electronic device may be provided in each of the pathways. Additionally, isolation circuits or devices can be inserted between signal lines to provide isolation between inputs, in the case of combining, or outputs, in the case of dividing. In one embodiment, multiple phase shift components are electrically connected to electronic devices in the electrical pathways. These phase shift components are selected so that a vector sum of the reflected signals from the inputs in combining and/or to the outputs in dividing is substantially minimized.

Abstract translation: 功率分配和/或功率合并电路具有基本上相等的输入和输出反射系数的输入，输出和至少三个电路径。 可以在每个路径中提供电子设备。 此外，隔离电路或器件可以插入信号线之间，以在组合的情况下提供输入之间的隔离，或者在分割的情况下输出。 在一个实施例中，多个相移元件电连接到电路中的电子器件。 选择这些相移分量，使得来自组合中的输入和/或分割中的输出的反射信号的向量和基本上最小化。

公开(公告)号：US20140368297A1

公开(公告)日：2014-12-18

申请号：US13922980

申请日：2013-06-20

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Ali M. Darwish ,  Hingloi Alfred Hung

IPC: H01P5/12 ,  H03F3/68

CPC classification number: H03F3/68 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F2203/21106

Abstract: Power-dividing and/or power-combining circuits have inputs, outputs, at least three electrical pathways, and at least three electronic devices, such as amplifiers, with substantially equal input and output reflection At least one of the electronic devices is in each of the electrical pathways. In one embodiment, multiple phase shift components, such as delay lines, are electrically connected to the electronic devices in each of the electrical pathways. These phase shift components are selected so that a vector sum of the reflected signals from the electronic devices to the inputs and/or the outputs is substantially minimized. In another embodiment, a serial bus extends from the inputs/outputs and at least three pathways in the circuit. The serial bus includes serially-connected impedance-providing components positioned among at least three pathways with the impedance-providing components increasing in impedance from one end to the other end of the serial bus in an amount sufficient to produce a substantially equal amount of power to each of the electronic devices and to substantially minimize input and output reflections.

Abstract translation: 功率分配和/或功率组合电路具有输入，输出，至少三个电路径，以及至少三个具有基本上相等的输入和输出反射的电子装置，例如放大器。至少一个电子装置在 电路。 在一个实施例中，诸如延迟线的多个相移分量电连接到每个电路径中的电子设备。 选择这些相移分量，使得从电子设备到输入和/或输出的反射信号的矢量和基本上最小化。 在另一个实施例中，串行总线从电路中的输入/输出和至少三个通路延伸。 串行总线包括位于至少三个通路之间的串联连接的阻抗提供组件，其中阻抗提供部件的阻抗从串行总线的一端增加到另一端，其量足以产生基本相等的功率 每个电子设备并且基本上最小化输入和输出反射。