公开(公告)号：US20010024866A1

公开(公告)日：2001-09-27

申请号：US09814390

申请日：2001-03-21

Applicant: U.S. Philips Corporation

Inventor： Darren T. Murley ,  Michael J. Trainor

IPC: H01L021/20 ,  H01L021/36 ,  H01L021/26 ,  H01L021/324 ,  H01L021/42 ,  H01L021/477 ,  H01L021/84

CPC classification number: H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8null) electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8null). The method comprising the steps of applying a foil (2) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (4) over a supporting substrate (1); and heating the semiconductor layer (4) so as to crystallise the semiconductor layer (4) from regions exposed to the CEM of the foil (2). The method may further comprise the step of providing a patterned barrier layer (3) between the foil (2) and the semiconductor layer (4) wherein the semiconductor layer (4) is crystallised from regions exposed through vias in the barrier layer (3) to the CEM of the foil (2). Also disclosed is a TFT (10) manufactured by the same, and an active matrix device (20) comprising a row and column array of active elements (22) wherein each element (22) is associated with such a TFT (10) connected to corresponding row (24) and column (23) conductors.

Abstract translation: 公开了一种制造TFT（10）的方法，其包括由半导体层（4），栅极绝缘层（7）和栅极绝缘层（7）形成的半导体沟道（6）连接的源极（8）和漏极（8“ 栅电极（8'）。 该方法包括以下步骤：施加包含结晶增强材料（CEM）的箔（2）并将半导体层（4）沉积在支撑衬底（1）上; 以及加热半导体层（4）以使半导体层（4）从暴露于箔（2）的CEM的区域结晶。 该方法还可以包括在箔（2）和半导体层（4）之间提供图案化阻挡层（3）的步骤，其中半导体层（4）从通过阻挡层（3）中的通孔暴露的区域结晶化， 到箔（2）的CEM。 还公开了由其制造的TFT（10）以及包括有源元件（22）的行和列阵列的有源矩阵器件（20），其中每个元件（22）与这样的TFT（10）相关联， 相应的行（24）和列（23）导体。