公开(公告)号：US10468494B2

公开(公告)日：2019-11-05

申请号：US15892671

申请日：2018-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Mou Lin ,  Chin-Chia Kuo ,  Ming-Hua Tsai ,  Su-Hua Tsai ,  Pai-Tsang Liu ,  Chiao-Yu Li ,  Chun-Ning Wu ,  Wei-Hsuan Chang

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/3215

Abstract: A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.

公开(公告)号：US20190252513A1

公开(公告)日：2019-08-15

申请号：US15892671

申请日：2018-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Mou Lin ,  Chin-Chia Kuo ,  Ming-Hua Tsai ,  Su-Hua Tsai ,  Pai-Tsang Liu ,  Chiao-Yu Li ,  Chun-Ning Wu ,  Wei-Hsuan Chang

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/66

Abstract: A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.