公开(公告)号：US20230261092A1

公开(公告)日：2023-08-17

申请号：US17694694

申请日：2022-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Hao-Ping Yan ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/7833 ,  H01L29/0607

Abstract: A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.

公开(公告)号：US20210217705A1

公开(公告)日：2021-07-15

申请号：US16737928

申请日：2020-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01L21/762 ,  H01L27/06

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

公开(公告)号：US20240266435A1

公开(公告)日：2024-08-08

申请号：US18120980

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Chin-Chia Kuo ,  Wei-Hsuan Chang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/6659

Abstract: A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.

公开(公告)号：US11114390B2

公开(公告)日：2021-09-07

申请号：US16737928

申请日：2020-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L23/522 ,  H01L27/06 ,  H01L23/00 ,  H01L49/02 ,  H01L21/762 ,  H01L27/08 ,  H01L21/3105

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

公开(公告)号：US20250015161A1

公开(公告)日：2025-01-09

申请号：US18237420

申请日：2023-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a substrate; a channel region disposed in the substrate; and a diffusion region disposed in the substrate on a side of the channel region. The diffusion region comprises a LDD region and a heavily doped region within the LDD region. A gate electrode is disposed over the channel region. The gate electrode partially overlaps with the LDD region. A spacer is disposed on a sidewall of the gate electrode. A gate oxide layer is disposed between the gate electrode and the channel region, between the gate electrode and the LDD region, and between the spacer and the LDD region. A silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.

公开(公告)号：US10468494B2

公开(公告)日：2019-11-05

申请号：US15892671

申请日：2018-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Mou Lin ,  Chin-Chia Kuo ,  Ming-Hua Tsai ,  Su-Hua Tsai ,  Pai-Tsang Liu ,  Chiao-Yu Li ,  Chun-Ning Wu ,  Wei-Hsuan Chang

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/3215

Abstract: A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.

公开(公告)号：US20240222455A1

公开(公告)日：2024-07-04

申请号：US18107516

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/7816 ,  H01L29/41725

Abstract: A high-voltage transistor includes a well region disposed in a semiconductor substrate, a gate structure disposed above the well region, a gate oxide layer disposed between the gate structure and the well region, a first drift region, and a second drift region. A first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer. A thickness of the second portion is greater than or equal to one eighth of a thickness of the first portion. The first drift region and the second drift region are disposed in the well region, at least partially located at two opposite sides of the gate structure, respectively, and disposed adjacent to the first portion and the second portion, respectively. A conductivity type of the first drift region is identical to that of the second drift region. A level-up shifting circuit includes the high-voltage transistor described above.

公开(公告)号：US20230006062A1

公开(公告)日：2023-01-05

申请号：US17366053

申请日：2021-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/78 ,  H01L29/45

Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

公开(公告)号：US20190252513A1

公开(公告)日：2019-08-15

申请号：US15892671

申请日：2018-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Mou Lin ,  Chin-Chia Kuo ,  Ming-Hua Tsai ,  Su-Hua Tsai ,  Pai-Tsang Liu ,  Chiao-Yu Li ,  Chun-Ning Wu ,  Wei-Hsuan Chang

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/66

Abstract: A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.

公开(公告)号：US11569380B2

公开(公告)日：2023-01-31

申请号：US17366053

申请日：2021-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

IPC: H01L29/78 ,  H01L29/45

Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.