公开(公告)号：US20180197749A1

公开(公告)日：2018-07-12

申请号：US15862564

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Fu-Shou Tsai ,  Wen-Chin Lin ,  Chun-Liang Liu

IPC: H01L21/321 ,  H01L27/108 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3105

Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

公开(公告)号：US10722998B2

公开(公告)日：2020-07-28

申请号：US15719515

申请日：2017-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

IPC: B24B37/24 ,  B24B37/22 ,  B24B37/26

Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

公开(公告)号：US20190070706A1

公开(公告)日：2019-03-07

申请号：US15719515

申请日：2017-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

IPC: B24B37/22 ,  B24B37/26

CPC classification number: B24B37/22 ,  B24B37/24 ,  B24B37/26 ,  B24D2205/00

Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

公开(公告)号：US10734276B2

公开(公告)日：2020-08-04

申请号：US15862564

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Fu-Shou Tsai ,  Wen-Chin Lin ,  Chun-Liang Liu

IPC: H01L21/768 ,  H01L27/108 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/762

Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

公开(公告)号：US09779989B1

公开(公告)日：2017-10-03

申请号：US15168095

申请日：2016-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Chun-Liang Liu

IPC: H01L21/00 ,  H01L21/768

CPC classification number: H01L21/7684 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76873

Abstract: A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.