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公开(公告)号：US20220209017A1
公开(公告)日：2022-06-30
申请号：US17159168
申请日：2021-01-27
发明人： Hung-Hsun Shuai , Chih-Jung Chen
IPC分类号： H01L29/788 , H01L29/06 , H01L29/08 , H01L29/423 , H01L21/265 , H01L21/762 , H01L21/28 , H01L29/66
摘要： A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.
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公开(公告)号：US11737265B2
公开(公告)日：2023-08-22
申请号：US17888511
申请日：2022-08-16
发明人： Chih-Jung Chen , Hung-Hsun Shuai
摘要： A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.
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公开(公告)号：US20220278238A1
公开(公告)日：2022-09-01
申请号：US17747976
申请日：2022-05-18
发明人： Hung-Hsun Shuai , Chih-Jung Chen
IPC分类号： H01L29/788 , H01L21/28 , H01L29/08 , H01L21/265 , H01L29/06 , H01L29/66 , H01L21/762 , H01L29/423
摘要： A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.
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公开(公告)号：US20240334693A1
公开(公告)日：2024-10-03
申请号：US18739352
申请日：2024-06-11
发明人： Yu-Jen Yeh , Hung-Hsun Shuai , Chih-Jung Chen
IPC分类号： H10B41/35 , H01L29/423 , H01L29/66 , H10B41/60
CPC分类号： H10B41/35 , H01L29/42328 , H01L29/66825 , H10B41/60
摘要： A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.
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公开(公告)号：US11705526B2
公开(公告)日：2023-07-18
申请号：US17747976
申请日：2022-05-18
发明人： Hung-Hsun Shuai , Chih-Jung Chen
IPC分类号： H01L29/788 , H01L21/265 , H01L21/762 , H01L29/06 , H01L29/08 , H01L21/28 , H01L29/423 , H10B41/30 , H10B41/10 , H01L29/66
CPC分类号： H01L29/7881 , H01L21/26513 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/40114 , H01L29/42328 , H01L29/66825
摘要： A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.
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公开(公告)号：US20230225120A1
公开(公告)日：2023-07-13
申请号：US17676209
申请日：2022-02-20
发明人： Yu-Jen Yeh , Hung-Hsun Shuai , Chih-Jung Chen
IPC分类号： H01L27/11524 , H01L27/11558 , H01L29/66 , H01L29/423
CPC分类号： H01L27/11524 , H01L27/11558 , H01L29/66825 , H01L29/42328
摘要： A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.
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公开(公告)号：US11456305B2
公开(公告)日：2022-09-27
申请号：US17005285
申请日：2020-08-27
发明人： Chih-Jung Chen , Hung-Hsun Shuai
IPC分类号： H01L21/00 , H01L27/11521 , H01L27/11565 , H01L27/11519 , H01L27/11568
摘要： A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.
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公开(公告)号：US20230171958A1
公开(公告)日：2023-06-01
申请号：US17565484
申请日：2021-12-30
发明人： Hung-Hsun Shuai , Yu-Jen Yeh , Chih-Jung Chen
IPC分类号： H01L27/11526 , G11C16/28 , G11C16/24
CPC分类号： H01L27/11526 , G11C16/28 , G11C16/24
摘要： A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.
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公开(公告)号：US20220415913A1
公开(公告)日：2022-12-29
申请号：US17888511
申请日：2022-08-16
发明人： Chih-Jung Chen , Hung-Hsun Shuai
IPC分类号： H01L27/11521 , H01L27/11565 , H01L27/11519 , H01L27/11568
摘要： A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.
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公开(公告)号：US11495693B2
公开(公告)日：2022-11-08
申请号：US17159168
申请日：2021-01-27
发明人： Hung-Hsun Shuai , Chih-Jung Chen
IPC分类号： H01L29/788 , H01L21/265 , H01L21/762 , H01L29/06 , H01L29/08 , H01L21/28 , H01L29/423 , H01L29/66
摘要： A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.
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