中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.014 seconds)

    Method for fabricating flash memory
    1.
    发明授权
    Method for fabricating flash memory 有权

    公开(公告)号：US11417734B2

    公开(公告)日：2022-08-16

    申请号：US16670870

    申请日：2019-10-31

    Applicant: United Microelectronics Corp.

    Inventor： Chih-Jung Chen ,  Yu-Jen Yeh

    IPC: H01L21/762 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105

    Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

    SMEICONDUCTOR MEMORY DEVICE
    2.
    发明公开
    SMEICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230171958A1

    公开(公告)日：2023-06-01

    申请号：US17565484

    申请日：2021-12-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Hsun Shuai ,  Yu-Jen Yeh ,  Chih-Jung Chen

    IPC: H01L27/11526 ,  G11C16/28 ,  G11C16/24

    CPC classification number: H01L27/11526 ,  G11C16/28 ,  G11C16/24

    Abstract: A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.

    Non-volatile memory device and method for fabricating the same
    3.
    发明授权
    Non-volatile memory device and method for fabricating the same 有权

    公开(公告)号：US11637188B2

    公开(公告)日：2023-04-25

    申请号：US17226431

    申请日：2021-04-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Jen Yeh ,  Chih-Jung Chen

    IPC: H10B41/30 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/265 ,  H01L21/28

    Abstract: An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

    FLASH MEMORY AND MANUFACTURING METHOD THEREOF
    4.
    发明公开
    FLASH MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240237335A9

    公开(公告)日：2024-07-11

    申请号：US17994009

    申请日：2022-11-25

    Applicant: United Microelectronics Corp.

    Inventor： Yu-Jen Yeh

    IPC: H01L29/76 ,  H01L29/423

    CPC classification number: H01L27/11553 ,  H01L29/42328

    Abstract: Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

    FLASH MEMORY AND MANUFACTURING METHOD THEREOF
    5.
    发明公开
    FLASH MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240138144A1

    公开(公告)日：2024-04-25

    申请号：US17994009

    申请日：2022-11-25

    Applicant: United Microelectronics Corp.

    Inventor： Yu-Jen Yeh

    IPC: H01L29/76 ,  H01L29/423

    CPC classification number: H01L27/11553 ,  H01L29/42328

    Abstract: Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240334693A1

    公开(公告)日：2024-10-03

    申请号：US18739352

    申请日：2024-06-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Jen Yeh ,  Hung-Hsun Shuai ,  Chih-Jung Chen

    IPC: H10B41/35 ,  H01L29/423 ,  H01L29/66 ,  H10B41/60

    CPC classification number: H10B41/35 ,  H01L29/42328 ,  H01L29/66825 ,  H10B41/60

    Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230225120A1

    公开(公告)日：2023-07-13

    申请号：US17676209

    申请日：2022-02-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Jen Yeh ,  Hung-Hsun Shuai ,  Chih-Jung Chen

    IPC: H01L27/11524 ,  H01L27/11558 ,  H01L29/66 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/42328

    Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

Patent Agency Ranking