公开(公告)号：US20180337000A1

公开(公告)日：2018-11-22

申请号：US15619108

申请日：2017-06-09

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen

IPC: H01G4/06 ,  H01G4/005 ,  H01L23/522

Abstract: A capacitor includes a first electrode, a dielectric, and a second electrode. The first electrode is located on a dielectric layer. The dielectric covers the sidewall and the top surface of the first electrode. The second electrode covers the dielectric and the dielectric layer, wherein the orthographic projection area of the second electrode on the dielectric layer is greater than the orthographic projection area of the first electrode on the dielectric layer. The capacitor of the invention has good reliability.

公开(公告)号：US20160020334A1

公开(公告)日：2016-01-21

申请号：US14483177

申请日：2014-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Han Jen

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L29/4234 ,  H01L29/66833

Abstract: The present invention provides a semiconductor structure, including a substrate, a gate dielectric layer disposed on the substrate, a charge storage layer disposed on the gate dielectric layer, and at least two poly silicon layers, disposed on the gate dielectric layer respectively, and covering parts of the charge storage layer simultaneously.

Abstract translation: 本发明提供了一种半导体结构，包括基板，设置在基板上的栅极介电层，设置在栅极电介质层上的电荷存储层和分别设置在栅极介电层上的至少两个多晶硅层，并且覆盖 部分电荷存储层同时进行。

公开(公告)号：US10373966B2

公开(公告)日：2019-08-06

申请号：US15264423

申请日：2016-09-13

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen ,  Chieh-Yu Tsai ,  Chun-Cheng Chiang

IPC: H01L27/112 ,  H01L49/02 ,  H01L21/28

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including an upper horizontal bar, a lower horizontal bar contiguous with the upper horizontal bar, and a step structure with a step height at which the two bars are contiguous, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the upper horizontal bar of each first poly-Si layer, and on the second silicide layer.

公开(公告)号：US20180076207A1

公开(公告)日：2018-03-15

申请号：US15264423

申请日：2016-09-13

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen ,  Chieh-Yu Tsai ,  Chun-Cheng Chiang

IPC: H01L27/112 ,  H01L49/02 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11253 ,  H01L28/20

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the convex portion of each first poly-Si layer, and on the second silicide layer.

公开(公告)号：US20170025429A1

公开(公告)日：2017-01-26

申请号：US14805484

申请日：2015-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Han Jen ,  Chao-Sheng Cheng

IPC: H01L27/115 ,  H01L49/02 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66 ,  H01L27/07 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L27/0629 ,  H01L27/11524 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.

Abstract translation: 半导体集成器件及其形成方法，半导体集成器件包括衬底，至少一个浅沟槽隔离，存储单元器件和多绝缘体 - 多晶硅电容器。 在基板上限定电容器区域和存储单元区域。 在衬底中形成至少一个浅沟槽隔离。 存储单元装置设置在存储单元区域中的至少一个浅沟槽隔离层上并且包括双多晶硅栅极。 多绝缘体 - 多晶硅电容器设置在电容器区域中的至少一个浅沟槽隔离上，其中多绝缘体 - 多晶硅电容器直接接触至少一个浅沟槽隔离。

公开(公告)号：US10600568B2

公开(公告)日：2020-03-24

申请号：US15619108

申请日：2017-06-09

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen

IPC: H01G4/06 ,  H01G4/005 ,  H01L23/522 ,  H01G4/012 ,  H01L49/02 ,  H01G4/12 ,  H01G4/08 ,  H01G4/33

Abstract: A capacitor includes a first electrode, a dielectric, and a second electrode. The first electrode is located on a dielectric layer. The dielectric covers the sidewall and the top surface of the first electrode. The second electrode covers the dielectric and the dielectric layer, wherein the orthographic projection area of the second electrode on the dielectric layer is greater than the orthographic projection area of the first electrode on the dielectric layer. The capacitor of the invention has good reliability.

公开(公告)号：US10079315B2

公开(公告)日：2018-09-18

申请号：US14483177

申请日：2014-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Han Jen

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L29/4234 ,  H01L29/66833

Abstract: The present invention provides a semiconductor structure, including a substrate, a gate dielectric layer disposed on the substrate, a charge storage layer disposed on the gate dielectric layer, and at least two poly silicon layers, disposed on the gate dielectric layer respectively, and covering parts of the charge storage layer simultaneously.

公开(公告)号：US09570456B1

公开(公告)日：2017-02-14

申请号：US14805484

申请日：2015-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Han Jen ,  Chao-Sheng Cheng

IPC: H01L27/07 ,  H01L27/115 ,  H01L49/02 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L27/0629 ,  H01L27/11524 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.

Abstract translation: 半导体集成器件及其形成方法，半导体集成器件包括衬底，至少一个浅沟槽隔离，存储单元器件和多绝缘体 - 多晶硅电容器。 在基板上限定电容器区域和存储单元区域。 在衬底中形成至少一个浅沟槽隔离。 存储单元装置设置在存储单元区域中的至少一个浅沟槽隔离层上并且包括双多晶硅栅极。 多绝缘体 - 多晶硅电容器设置在电容器区域中的至少一个浅沟槽隔离上，其中多绝缘体 - 多晶硅电容器直接接触至少一个浅沟槽隔离。