公开(公告)号：US20140242770A1

公开(公告)日：2014-08-28

申请号：US13773635

申请日：2013-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hung Huang ,  Jie-Ning Yang ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Po-Jui Liao ,  Shih-Chang Chang

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/76801 ,  H01L21/76834 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。

公开(公告)号：US20150228788A1

公开(公告)日：2015-08-13

申请号：US14179563

申请日：2014-02-13

Applicant: United Microelectronics Corp.

Inventor： Chun-Feng Chen ,  Wen-Yu Yang ,  Yu-Cheng Tung ,  Chun-Hsien Huang ,  Hui-Shen Shih ,  Shih-Chang Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/76832 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

Abstract: A stress memorization process including the following step is provided. A gate is formed on a substrate. A low-k dielectric layer with a dielectric constant lower than 3 is formed to entirely cover the gate and the substrate. A stress layer is formed to entirely cover the low-k dielectric layer. The stress layer and the low-k dielectric layer are removed. Moreover, a semiconductor structure including a contact etch stop layer is provided. A gate is disposed on a substrate. A porous layer entirely covers the gate and the substrate. A contact etch stop layer entirely covers the porous layer, wherein the thickness of the porous layer is thinner than the thickness of the contact etch stop layer.

Abstract translation: 提供包括以下步骤的应力记忆过程。 栅极形成在基板上。 形成介电常数低于3的低k电介质层，以完全覆盖栅极和衬底。 形成应力层以完全覆盖低k电介质层。 去除应力层和低k电介质层。 此外，提供了包括接触蚀刻停止层的半导体结构。 栅极设置在基板上。 多孔层完全覆盖栅极和衬底。 接触蚀刻停止层完全覆盖多孔层，其中多孔层的厚度比接触蚀刻停止层的厚度薄。

公开(公告)号：US09240459B2

公开(公告)日：2016-01-19

申请号：US13773635

申请日：2013-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hung Huang ,  Jie-Ning Yang ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Po-Jui Liao ,  Shih-Chang Chang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/76801 ,  H01L21/76834 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。