公开(公告)号：US20170236899A1

公开(公告)日：2017-08-17

申请号：US15587378

申请日：2017-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Su-Hwa Tsai

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L29/0661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66613 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

公开(公告)号：US09806150B2

公开(公告)日：2017-10-31

申请号：US15587378

申请日：2017-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Su-Hwa Tsai

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/0661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66613 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

公开(公告)号：US09680010B1

公开(公告)日：2017-06-13

申请号：US15015142

申请日：2016-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Su-Hwa Tsai

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/66613 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

公开(公告)号：US09136375B2

公开(公告)日：2015-09-15

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US20150137228A1

公开(公告)日：2015-05-21

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。