公开(公告)号：US20170162721A1

公开(公告)日：2017-06-08

申请号：US14989814

申请日：2016-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ke-Feng Lin ,  Hsuan-Po Liao ,  Ming-Shun Hsu ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shih-Teng Huang

IPC: H01L29/861 ,  H01L29/06

CPC classification number: H01L29/8615 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/8613

Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

公开(公告)号：US20180114858A1

公开(公告)日：2018-04-26

申请号：US15631820

申请日：2017-06-23

Applicant: United Microelectronics Corp.

Inventor： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/36 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US10276652B1

公开(公告)日：2019-04-30

申请号：US16005652

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Ke-Feng Lin ,  Ming-Tsung Lee ,  Shih-Teng Huang ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shu-Wen Lin

IPC: H01L29/06 ,  H01L29/872

Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.

公开(公告)号：US09741826B1

公开(公告)日：2017-08-22

申请号：US15299268

申请日：2016-10-20

Applicant: United Microelectronics Corp.

Inventor： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

Abstract: A transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on the substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US09997643B2

公开(公告)日：2018-06-12

申请号：US14989814

申请日：2016-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ke-Feng Lin ,  Hsuan-Po Liao ,  Ming-Shun Hsu ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shih-Teng Huang

IPC: H01L29/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/8615 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/8613

Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

公开(公告)号：US09954099B1

公开(公告)日：2018-04-24

申请号：US15631820

申请日：2017-06-23

Applicant: United Microelectronics Corp.

Inventor： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/36 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US09431239B1

公开(公告)日：2016-08-30

申请号：US14809278

申请日：2015-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Nien-Chung Li ,  Ching-Nan Hwang ,  Shih-Teng Huang ,  Ming-Yen Liu

IPC: H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/167 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/823462 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate; forming a thermal oxide layer on the substrate and the doped region; removing the thermal oxide layer to form a first recess; forming an epitaxial layer on the substrate and in the first recess; and forming a gate dielectric layer in the epitaxial layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底中形成掺杂区域; 在衬底和掺杂区上形成热氧化层; 去除热氧化物层以形成第一凹槽; 在所述基板和所述第一凹部中形成外延层; 以及在所述外延层中形成栅极电介质层。

公开(公告)号：US09136375B2

公开(公告)日：2015-09-15

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US20150137228A1

公开(公告)日：2015-05-21

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。