公开(公告)号：US20150200192A1

公开(公告)日：2015-07-16

申请号：US14153079

申请日：2014-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Yao-Hung Huang ,  Chien-Ting Lin ,  Ming-Te Wei

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L27/0922 ,  H01L21/02164 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385

Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

Abstract translation: 本发明提供一种半导体结构，包括其上设置有介电层的基板，限定在其上的第一器件区域和第二器件区域，设置在第一器件区域内的衬底中的至少一个第一沟槽，至少一个第二 沟槽和设置在第二器件区域内的衬底中的至少一个第三沟槽，设置在第二沟槽和第三沟槽中的功函数层，其中功函数层部分地覆盖第二沟槽的侧壁，并且完全覆盖 第三沟槽的侧壁和设置在第二沟槽和第三沟槽中的第一材料层，其中第一材料层覆盖设置在第二沟槽的部分侧壁上的功函数层，并且完全覆盖设置在第二沟槽上的功函数层 第三沟槽的侧壁。

公开(公告)号：US09318490B2

公开(公告)日：2016-04-19

申请号：US14153079

申请日：2014-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Yao-Hung Huang ,  Chien-Ting Lin ,  Ming-Te Wei

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/02164 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385

Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

Abstract translation: 本发明提供一种半导体结构，包括其上设置有介电层的基板，限定在其上的第一器件区域和第二器件区域，设置在第一器件区域内的衬底中的至少一个第一沟槽，至少一个第二 沟槽和设置在第二器件区域内的衬底中的至少一个第三沟槽，设置在第二沟槽和第三沟槽中的功函数层，其中功函数层部分地覆盖第二沟槽的侧壁，并且完全覆盖 第三沟槽的侧壁和设置在第二沟槽和第三沟槽中的第一材料层，其中第一材料层覆盖设置在第二沟槽的部分侧壁上的功函数层，并且完全覆盖设置在第二沟槽上的功函数层 第三沟槽的侧壁。