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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140319613A1

    公开(公告)日：2014-10-30

    申请号：US13873261

    申请日：2013-04-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Ning He ,  Lu-An Chen ,  Tien-Hao Tang

    IPC: H01L23/552

    CPC classification number: H01L27/0248 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816

    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

    Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，在栅极的相应两侧在衬底中形成的漏极和源极以及形成在源极中的掺杂区域。 漏极和源极包括第一导电类型，并且掺杂区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160043216A1

    公开(公告)日：2016-02-11

    申请号：US14454739

    申请日：2014-08-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L29/78 ,  H01L29/10

    CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

    Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

    Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09343567B2

    公开(公告)日：2016-05-17

    申请号：US14454739

    申请日：2014-08-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/02 ,  H01L29/10

    CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

    Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

    Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。

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