公开(公告)号：US20240312527A1

公开(公告)日：2024-09-19

申请号：US18677836

申请日：2024-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning Peng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: G11C16/24 ,  G11C16/08 ,  H01L29/788 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/24 ,  G11C16/08 ,  H01L29/7881 ,  H10B41/10 ,  H10B41/27

Abstract: A method for forming semiconductor structure with wave shaped erase gate, the method including the steps: forming a floating gate having staggered islands on a substrate, forming a erase gate having a wave shape on the substrate at a first side of the floating gate, and forming a word line having the wave shape on the substrate at a second side of the floating gate opposite to the first side.

公开(公告)号：US20220230689A1

公开(公告)日：2022-07-21

申请号：US17151226

申请日：2021-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning Peng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: G11C16/24 ,  G11C16/08 ,  H01L29/788 ,  H01L27/11556 ,  H01L27/11519

Abstract: An electrically erasable programmable read only memory (EEPROM) includes a substrate, bit lines, a row of erase gate and a row of floating gates. The bit lines are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the bit lines. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.

公开(公告)号：US20230033836A1

公开(公告)日：2023-02-02

申请号：US17960789

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US20240397712A1

公开(公告)日：2024-11-28

申请号：US18792499

申请日：2024-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

公开(公告)号：US20230301083A1

公开(公告)日：2023-09-21

申请号：US18203054

申请日：2023-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/42328 ,  H01L29/7833 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7881

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

公开(公告)号：US12082405B2

公开(公告)日：2024-09-03

申请号：US18203054

申请日：2023-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

公开(公告)号：US11832444B2

公开(公告)日：2023-11-28

申请号：US17960789

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L29/423 ,  H01L29/66 ,  H10B41/30 ,  H01L29/78 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US11706915B2

公开(公告)日：2023-07-18

申请号：US17381219

申请日：2021-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US20220406800A1

公开(公告)日：2022-12-22

申请号：US17381219

申请日：2021-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).