公开(公告)号：US20130058145A1

公开(公告)日：2013-03-07

申请号：US13604308

申请日：2012-09-05

申请人： Hak-soo YU ,  Uk-song KANG ,  Chul-woo PARK ,  Joo-sun CHOI ,  Hong-Sun HWANG

发明人： Hak-soo YU ,  Uk-song KANG ,  Chul-woo PARK ,  Joo-sun CHOI ,  Hong-Sun HWANG

IPC分类号： G11C29/00 ,  G11C15/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/783 ,  G11C2029/0409 ,  G11C2029/4402

摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

摘要翻译： 半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

公开(公告)号：US20130039135A1

公开(公告)日：2013-02-14

申请号：US13569636

申请日：2012-08-08

申请人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

发明人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

IPC分类号： G11C7/22

CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

摘要： A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

公开(公告)号：US20120138927A1

公开(公告)日：2012-06-07

申请号：US13312000

申请日：2011-12-06

申请人： Uk-song KANG

发明人： Uk-song KANG

IPC分类号： H01L23/00

CPC分类号： G01R31/318513 ,  H01L22/14 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a stacked structure including through-silicon-vias (TSVs) and a method of testing the semiconductor device. The semiconductor device includes a first semiconductor layer, one or more second semiconductor layers stacked on the first semiconductor layer, and a plurality of input through-silicon-vias (TSVs) to transmit signals from a plurality of input pads, respectively. In a test mode, a test signal from the plurality of input pads is transmitted through at least two test paths, and the test signal transmitted through each of the test paths is output as a test result with respect to each of the plurality of input TSVs through an output pad.

摘要翻译： 具有包括贯通硅通孔（TSV）的层叠结构的半导体器件和测试半导体器件的方法。 半导体器件包括第一半导体层，堆叠在第一半导体层上的一个或多个第二半导体层以及分别从多个输入焊盘传输信号的多个输入通硅通孔（TSV）。 在测试模式中，通过至少两个测试路径传输来自多个输入焊盘的测试信号，并且通过每个测试路径发送的测试信号作为关于多个输入TSV中的每一个的测试结果被输出 通过输出板。

公开(公告)号：US20090091962A1

公开(公告)日：2009-04-09

申请号：US12238720

申请日：2008-09-26

申请人： Hoe-ju CHUNG ,  Jung-bae LEE ,  Uk-song KANG

发明人： Hoe-ju CHUNG ,  Jung-bae LEE ,  Uk-song KANG

IPC分类号： G11C5/02 ,  H01L21/00

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

摘要翻译： 多芯片存储器件包括传送输入/输出信号的传输存储器芯片，每个包括具有指定存储体的存储器阵列的堆叠多个存储器芯片，以及通过存储芯片堆栈从传输存储器芯片向上延伸的信号路径 通信输入/输出信号，其中堆叠的多个存储器芯片中的每个存储器芯片的每个存储体通常被寻址以在读取操作期间提供读取数据，并且在写入操作期间接收写入数据，并且在堆叠的多个存储器内垂直对准 筹码

公开(公告)号：US20090039492A1

公开(公告)日：2009-02-12

申请号：US12123583

申请日：2008-05-20

申请人： Uk-song KANG ,  Jung-bae LEE ,  Hoe-ju CHUNG

发明人： Uk-song KANG ,  Jung-bae LEE ,  Hoe-ju CHUNG

IPC分类号： H01L23/02

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2224/05599

摘要： A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

摘要翻译： 半导体存储器件包括堆叠的多个插入器芯片，每个插入器芯片放置较小的对应的存储器芯片，其中堆叠的多个插入器芯片中的最下层插入器芯片安装在缓冲芯片上。 堆叠的多个插入器芯片中的每一个包括具有连接衬垫对应的存储器件的中心部分和具有多个穿通硅通孔（TSV）的外围部分。 堆叠的多个插入器芯片中的相邻插入器芯片的相应多个TSV通过垂直连接元件连接，以形成从相应存储器芯片向缓冲器芯片传送写入数据和从其读取数据的多个内部信号路径。