公开(公告)号：US06204140B1

公开(公告)日：2001-03-20

申请号：US09275337

申请日：1999-03-24

申请人： Ulrike Gruening ,  Jochen Beintner ,  Scott Halle ,  Jack A. Mandelman ,  Carl J. Radens ,  Juergen Wittmann ,  Jeffrey J. Welser

发明人： Ulrike Gruening ,  Jochen Beintner ,  Scott Halle ,  Jack A. Mandelman ,  Carl J. Radens ,  Juergen Wittmann ,  Jeffrey J. Welser

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10861

摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.

摘要翻译： 一种方法包括在半导体本体中形成沟槽电容器。 在电容器的上部形成凹部，该凹槽在半导体本体中具有侧壁。 第一材料沉积在凹槽的侧壁和底部上方。 第二种材料沉积在第一种材料上。 在第二材料上提供面罩。 掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。 第二材料的暴露的下部部分的部分是选择性地去除，同时留下基本未蚀刻的暴露的第一材料的下部。 选择性地去除半导体主体的第一材料和下部的暴露部分。 隔离区形成在半导体本体的去除部分中。 所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分， 第二材料的部分。 在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。 在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。 通过这种方法，允许更大的掩模不对准公差。

公开(公告)号：US06320215B1

公开(公告)日：2001-11-20

申请号：US09359292

申请日：1999-07-22

申请人： Gary Bronner ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Gary Bronner ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/1087 ,  H01L27/10876

摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.

摘要翻译： 一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。 侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。 制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件 在侧壁上的刻面晶体区域上。 小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

公开(公告)号：US06759291B2

公开(公告)日：2004-07-06

申请号：US10045499

申请日：2002-01-14

申请人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

发明人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

IPC分类号： H01L218234

CPC分类号： H01L27/10867

摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

摘要翻译： 一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。 沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。 控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。 此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。 唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。 衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形 形结构。 此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

公开(公告)号：US06369419B1

公开(公告)日：2002-04-09

申请号：US09603657

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

发明人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

IPC分类号： H01L2994

CPC分类号： H01L27/10867

摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

摘要翻译： 一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。 沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。 控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。 此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。 唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。 衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形 形结构。 此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

公开(公告)号：US06339241B1

公开(公告)日：2002-01-15

申请号：US09602426

申请日：2000-06-23

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Ulrike Gruening

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Ulrike Gruening

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

公开(公告)号：US6153902A

公开(公告)日：2000-11-28

申请号：US374687

申请日：1999-08-16

申请人： Toshiharu Furukawa ,  Ulrike Gruening ,  David V. Horak ,  Jack A. Mandelman ,  Carl J. Radens ,  Thomas S. Rupp

发明人： Toshiharu Furukawa ,  Ulrike Gruening ,  David V. Horak ,  Jack A. Mandelman ,  Carl J. Radens ,  Thomas S. Rupp

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.

摘要翻译： 动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。 使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。 信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域 沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体 并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

公开(公告)号：US06630379B2

公开(公告)日：2003-10-07

申请号：US10011556

申请日：2001-11-06

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Ulrike Gruening

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Ulrike Gruening

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

摘要翻译： 一种存储单元结构，包括平面半导体衬底。 深沟槽位于半导体衬底中。 深沟槽具有多个侧壁和底部。 存储电容器位于深沟槽的底部。 垂直晶体管向下延伸存储电容器上方的深沟槽的至少一个侧壁。 晶体管具有在邻近深沟槽的衬底的平面中延伸的源极扩散。 隔离层向下延伸与垂直晶体管相对的深沟槽的至少另一侧壁。 浅沟槽隔离区沿垂直晶体管延伸的横向于侧壁的方向沿着衬底的表面延伸。 栅极导体在深沟槽内延伸。 一条字线延伸穿过深沟槽并连接到栅极导体。 位线延伸在衬底的表面平面之上，并且具有与浅沟槽隔离区之间的源极扩散的接触。

公开(公告)号：US06573137B1

公开(公告)日：2003-06-03

申请号：US09603442

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Wolfgang Bergner ,  Gary B. Bronner ,  Ulrike Gruening ,  Stephan Kudelka ,  Alexander Michaelis ,  Larry Nesbit ,  Carl J. Radens ,  Till Schloesser ,  Helmut Tews

发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Wolfgang Bergner ,  Gary B. Bronner ,  Ulrike Gruening ,  Stephan Kudelka ,  Alexander Michaelis ,  Larry Nesbit ,  Carl J. Radens ,  Till Schloesser ,  Helmut Tews

IPC分类号： H01L218242

CPC分类号： H01L27/10864

摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

摘要翻译： 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。 屏蔽材料沉积在存储电容器的节点导体上方。 一层硅沉积在阻挡材料上。 掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：US06255158B1

公开(公告)日：2001-07-03

申请号：US09667652

申请日：2000-09-22

申请人： Toshiharu Furukawa ,  Ulrike Gruening ,  David V. Horak ,  Jack A. Mandelman ,  Carl J. Radens ,  Thomas S. Rupp

发明人： Toshiharu Furukawa ,  Ulrike Gruening ,  David V. Horak ,  Jack A. Mandelman ,  Carl J. Radens ,  Thomas S. Rupp

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.

摘要翻译： 动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。 使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。 信号传送装置包括耦合到信号存储节点并且从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域， 在所述第一扩散区域和所述第二扩散区域之间沿着所述沟槽的侧壁延伸的沟道区域，沿着从所述第一扩散区域延伸到所述第二扩散区域的所述沟槽的侧壁形成的栅极绝缘体，填充所述沟槽的栅极导体， 具有顶表面，并且字线具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

公开(公告)号：US06194755B1

公开(公告)日：2001-02-27

申请号：US09102471

申请日：1998-06-22

申请人： Jeffrey P. Gambino ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Jeffrey P. Gambino ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L2120

CPC分类号： H01L27/10861

摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而可以减少接地规则存储单元布局和/或降低单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。