-
公开(公告)号:US11037869B2
公开(公告)日:2021-06-15
申请号:US16690143
申请日:2019-11-21
发明人: Fu-Yang Chen , Chun-Hsien Chien , Cheng-Hui Wu , Wei-Ti Lin
IPC分类号: H01L21/48 , H01L23/498
摘要: A method of preparing a package structure is provided, which includes providing a carrier plate including a supporting layer, a first release layer, and a first metal layer; forming a first dielectric layer over the first metal layer, the first dielectric layer having a plurality of holes, each of the holes having an end portion substantially coplanar with each other at a same plane; forming a plurality of conductive protrusions filling the holes, each of the conductive protrusions having a first end and a second end opposite thereto; forming a circuit layer structure including at least one circuit layer and at least one second dielectric layer, the circuit layer being connected to the second end, the second dielectric layer being disposed over the circuit layer; removing the carrier plate; and removing a portion of the first dielectric layer to expose the conductive protrusions. A package structure is also provided.
-
公开(公告)号:US20200163215A1
公开(公告)日:2020-05-21
申请号:US16221587
申请日:2018-12-17
发明人: Wen-Liang Yeh , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
摘要: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
-
公开(公告)号:US20200161518A1
公开(公告)日:2020-05-21
申请号:US16281108
申请日:2019-02-21
发明人: Yi-Cheng Lin , Yu-Hua Chen , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
IPC分类号: H01L33/62 , H01L33/52 , H01L23/498 , H01L23/538 , H01L23/31
摘要: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
-
公开(公告)号:US20210057320A1
公开(公告)日:2021-02-25
申请号:US16690143
申请日:2019-11-21
发明人: Fu-Yang Chen , Chun-Hsien Chien , Cheng-Hui Wu , Wei-Ti Lin
IPC分类号: H01L23/498 , H01L21/48
摘要: A method of preparing a package structure is provided, which includes providing a carrier plate including a supporting layer, a first release layer, and a first metal layer; forming a first dielectric layer over the first metal layer, the first dielectric layer having a plurality of holes, each of the holes having an end portion substantially coplanar with each other at a same plane; forming a plurality of conductive protrusions filling the holes, each of the conductive protrusions having a first end and a second end opposite thereto; forming a circuit layer structure including at least one circuit layer and at least one second dielectric layer, the circuit layer being connected to the second end, the second dielectric layer being disposed over the circuit layer; removing the carrier plate; and removing a portion of the first dielectric layer to expose the conductive protrusions. A package structure is also provided.
-
公开(公告)号:US10660202B1
公开(公告)日:2020-05-19
申请号:US16221587
申请日:2018-12-17
发明人: Wen-Liang Yeh , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
IPC分类号: H05K1/00 , H05K1/02 , H05K1/03 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/02 , H05K3/10 , H05K3/30 , H05K3/46 , H05K3/28 , H05K3/34
摘要: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
-
公开(公告)号:US11251350B2
公开(公告)日:2022-02-15
申请号:US16281108
申请日:2019-02-21
发明人: Yi-Cheng Lin , Yu-Hua Chen , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
IPC分类号: H01L33/62 , H01L33/52 , H01L23/538 , H01L23/498 , H01L23/31
摘要: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
-
公开(公告)号:US10461146B1
公开(公告)日:2019-10-29
申请号:US16151351
申请日:2018-10-04
发明人: Wen-Liang Yeh , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
IPC分类号: H01L21/02 , H01L49/02 , H01L23/00 , H01L23/522
摘要: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.
-
-
-
-
-
-