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公开(公告)号：US20240206150A1
公开(公告)日：2024-06-20
申请号：US18545163
申请日：2023-12-19
发明人： Koji SAKUI , Yoshihisa IWATA , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/408 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4087 , G11C11/4096
摘要： A memory device is formed with at least one memory array, the memory array being formed with a plurality of pages and a plurality of bit lines, each page being formed with a plurality of memory cells arranged in a row direction on a substrate in a plan view, the plurality of memory cells being connected to the bit lines disposed in a column direction. Each of the memory cells included in each of the pages includes a semiconductor base material, a first impurity region and a second impurity region positioned in respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer. In the memory cell, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first and second gate conductor layers is connected to a word line, and the other is connected to a plate line. A page erase operation, a page write operation, and a page read operation are performed by controlling a voltage applied to each of the source line, the bit line, the word line, and the plate line. At least one of the bit lines and one of the pages are selected in the page erase operation, the page write operation, and the page read operation, and an erase operation on the memory cell connected to both the bit line and the page thus selected, a write operation of storage data of the sense amplifier circuit to the memory cell, or a read operation from the memory cell to the sense amplifier circuit is executed.
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公开(公告)号：US20240321343A1
公开(公告)日：2024-09-26
申请号：US18609198
申请日：2024-03-19
发明人： Koji SAKUI , Yoshihisa IWATA , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： G11C11/4096 , G11C5/06 , G11C11/4094 , H10B12/00
CPC分类号： G11C11/4096 , G11C5/063 , G11C11/4094 , H10B12/20 , H10B12/50
摘要： In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity layer and a second impurity layer at both ends in an extension direction of the semiconductor base, and at least two (first and second) gate conductor layers. The first impurity layer is connected to a source line, the second impurity layer to a bit line, one of the first or second gate conductor layer to a selection gate line, and the other to a plate line. Voltages applied to the source line, bit line, selection gate line, and plate line are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have logic storage data that is at least three-valued.
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