公开(公告)号：US12266723B2

公开(公告)日：2025-04-01

申请号：US18596643

申请日：2024-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

公开(公告)号：US10229995B2

公开(公告)日：2019-03-12

申请号：US15668719

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US12176403B2

公开(公告)日：2024-12-24

申请号：US17737041

申请日：2022-05-05

Applicant: United Microelectronics Corp.

Inventor： Chi-Hsiao Chen ,  Tzyy-Ming Cheng ,  Wei Jen Chen ,  Kai Lin Lee

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

公开(公告)号：US20190172949A1

公开(公告)日：2019-06-06

申请号：US16252521

申请日：2019-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US20230361206A1

公开(公告)日：2023-11-09

申请号：US18221409

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

公开(公告)号：US20190027602A1

公开(公告)日：2019-01-24

申请号：US15668719

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen ,  Ting-Hsuan Kang ,  Ren-Yu He ,  Hung-Wen Huang ,  Chi-Hsiao Chen ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

公开(公告)号：US12289900B2

公开(公告)日：2025-04-29

申请号：US17335049

申请日：2021-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H10D30/47 ,  H10D30/01 ,  H10D62/85

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

公开(公告)号：US20220359740A1

公开(公告)日：2022-11-10

申请号：US17335049

申请日：2021-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

公开(公告)号：US20180358453A1

公开(公告)日：2018-12-13

申请号：US15642360

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Wen Huang ,  Kai-Lin Lee ,  Ren-Yu He ,  Chi-Hsiao Chen ,  Ting-Hsuan Kang ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/66977 ,  H01L21/28088 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.

公开(公告)号：US20240213361A1

公开(公告)日：2024-06-27

申请号：US18596643

申请日：2024-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiao Chen ,  Kai-Lin Lee

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.