公开(公告)号：US10340282B1

公开(公告)日：2019-07-02

申请号：US15895886

申请日：2018-02-13

Applicant: United Microelectronics Corp.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang ,  An-Hsiu Cheng ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Chia-Hui Huang ,  Chih-Yao Wang ,  Zi-Jun Liu ,  Chih-Hao Pan

IPC: H01L21/18 ,  H01L27/1157 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.