公开(公告)号：US20230238058A1

公开(公告)日：2023-07-27

申请号：US17680264

申请日：2022-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen-Yang Hsueh ,  Ling-Hsiu Chou ,  Chih-Yang Hsu

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/3427 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/0483

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

公开(公告)号：US20210217866A1

公开(公告)日：2021-07-15

申请号：US16793930

申请日：2020-02-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen Yang Hsueh ,  Ling Hsiu Chou ,  Chih-Yang Hsu

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

公开(公告)号：US12119053B2

公开(公告)日：2024-10-15

申请号：US17680264

申请日：2022-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen-Yang Hsueh ,  Ling-Hsiu Chou ,  Chih-Yang Hsu

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/0483

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

公开(公告)号：US20240114688A1

公开(公告)日：2024-04-04

申请号：US17990738

申请日：2022-11-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Ling Hsiu Chou ,  Jen Yang Hsueh ,  Chih-Yang Hsu

IPC: H10B43/30 ,  H10B41/30

CPC classification number: H01L27/11568 ,  H01L27/11521

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

公开(公告)号：US11532716B2

公开(公告)日：2022-12-20

申请号：US16793930

申请日：2020-02-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen Yang Hsueh ,  Ling Hsiu Chou ,  Chih-Yang Hsu

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66 ,  G11C16/16 ,  G11C16/14

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

公开(公告)号：US10340282B1

公开(公告)日：2019-07-02

申请号：US15895886

申请日：2018-02-13

Applicant: United Microelectronics Corp.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang ,  An-Hsiu Cheng ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Chia-Hui Huang ,  Chih-Yao Wang ,  Zi-Jun Liu ,  Chih-Hao Pan

IPC: H01L21/18 ,  H01L27/1157 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.