公开(公告)号：US20220336606A1

公开(公告)日：2022-10-20

申请号：US17853954

申请日：2022-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US10199385B1

公开(公告)日：2019-02-05

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US20190378846A1

公开(公告)日：2019-12-12

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US20190043877A1

公开(公告)日：2019-02-07

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/11568 ,  H01L29/423

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US11600709B2

公开(公告)日：2023-03-07

申请号：US17853954

申请日：2022-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US20220271137A1

公开(公告)日：2022-08-25

申请号：US17219829

申请日：2021-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US11362186B2

公开(公告)日：2022-06-14

申请号：US16831846

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Kuo-Lung Li ,  Chih-Hao Pan ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chi-Cheng Huang

IPC: H01L29/423 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/28

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.

公开(公告)号：US20210265474A1

公开(公告)日：2021-08-26

申请号：US16831846

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Kuo-Lung Li ,  Chih-Hao Pan ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chi-Cheng Huang

IPC: H01L29/423 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.

公开(公告)号：US11417742B1

公开(公告)日：2022-08-16

申请号：US17219829

申请日：2021-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US11374109B2

公开(公告)日：2022-06-28

申请号：US16670890

申请日：2019-10-31

Applicant: United Microelectronics Corp.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/66 ,  H01L27/1157

Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.