公开(公告)号：US09966382B2

公开(公告)日：2018-05-08

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11543 ,  H01L27/11563

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US10720440B2

公开(公告)日：2020-07-21

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L27/11543 ,  H01L27/11563 ,  H01L21/28 ,  H01L29/788

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US20180053771A1

公开(公告)日：2018-02-22

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US10580780B2

公开(公告)日：2020-03-03

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L23/62 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/28

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US10340282B1

公开(公告)日：2019-07-02

申请号：US15895886

申请日：2018-02-13

Applicant: United Microelectronics Corp.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang ,  An-Hsiu Cheng ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Chia-Hui Huang ,  Chih-Yao Wang ,  Zi-Jun Liu ,  Chih-Hao Pan

IPC: H01L21/18 ,  H01L27/1157 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

公开(公告)号：US20190378846A1

公开(公告)日：2019-12-12

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US20180211966A1

公开(公告)日：2018-07-26

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11543 ,  H01L29/792 ,  H01L27/11563 ,  H01L29/78

CPC classification number: H01L27/1157 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.