公开(公告)号：US12096704B2

公开(公告)日：2024-09-17

申请号：US18383473

申请日：2023-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan Zhou ,  Xian Feng Du ,  Guoan Du ,  Guohai Zhang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

公开(公告)号：US11723295B2

公开(公告)日：2023-08-08

申请号：US17551214

申请日：2021-12-15

Applicant: United Microelectronics Corp.

Inventor： Hai Tao Liu ,  Li Li Ding ,  Yao-Hung Liu ,  Guoan Du ,  Qi Lu Li ,  Chunlei Wan ,  Yi Yu Lin ,  Yuchao Chen ,  Huakai Li ,  Hung-Yueh Chen

IPC: H01L45/00 ,  H01L27/24 ,  H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8833 ,  H10B63/80 ,  H10N70/028 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/841

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

公开(公告)号：US11844291B2

公开(公告)日：2023-12-12

申请号：US17353757

申请日：2021-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan Zhou ,  Xian Feng Du ,  Guoan Du ,  Guohai Zhang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

公开(公告)号：US20220109104A1

公开(公告)日：2022-04-07

申请号：US17551214

申请日：2021-12-15

Applicant: United Microelectronics Corp.

Inventor： Hai Tao Liu ,  Li Li Ding ,  Yao-Hung Liu ,  Guoan Du ,  Qi Lu Li ,  Chunlei Wan ,  Yi Yu Lin ,  Yuchao Chen ,  Huakai Li ,  Hung-Yueh Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

公开(公告)号：US11239419B2

公开(公告)日：2022-02-01

申请号：US16505190

申请日：2019-07-08

Applicant: United Microelectronics Corp.

Inventor： Hai Tao Liu ,  Li Li Ding ,  Yao-Hung Liu ,  Guoan Du ,  Qi Lu Li ,  Chunlei Wan ,  Yi Yu Lin ,  Yuchao Chen ,  Huakai Li ,  Hung-Yueh Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

公开(公告)号：US09799705B1

公开(公告)日：2017-10-24

申请号：US15297164

申请日：2016-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen ,  Guoan Du

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

CPC classification number: H01L27/2436 ,  H01L21/76877 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.