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公开(公告)号：US11804253B2
公开(公告)日：2023-10-31
申请号：US17273990
申请日：2019-09-06
发明人： Kian Ping Loh , Sock Mui Poh
IPC分类号： G11C16/04 , G11C11/22 , C23C14/06 , C23C14/30 , C23C14/54 , C23C14/56 , H01L21/02 , H10N70/00 , H01L29/872
CPC分类号： G11C11/22 , C23C14/0623 , C23C14/30 , C23C14/541 , C23C14/542 , C23C14/56 , H01L21/02568 , H10N70/028 , H10N70/841 , H10N70/8825 , H01L29/872
摘要： A continuous thin film comprises a metal chalcogenide, wherein the metal is selected from the periodic groups 13 or 14 and the chalcogen is: sulphur (S), selenide (Se), or tellurium (Te), and wherein the thin film has a thickness of less than 20 mm. Methods of forming the continuous thin film involve thermally evaporating precursors to form a thin film on the surface of a substrate. In a particular embodiment, molecular beam epitaxy (MBE) is used to grow indium selenide (In2Se3) thin film from two precursors (In2Se3 and Se) and the thin film is used to fabricate a ferroelectric resistive memory device.
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公开(公告)号：US11723295B2
公开(公告)日：2023-08-08
申请号：US17551214
申请日：2021-12-15
发明人： Hai Tao Liu , Li Li Ding , Yao-Hung Liu , Guoan Du , Qi Lu Li , Chunlei Wan , Yi Yu Lin , Yuchao Chen , Huakai Li , Hung-Yueh Chen
CPC分类号： H10N70/8833 , H10B63/80 , H10N70/028 , H10N70/24 , H10N70/826 , H10N70/8265 , H10N70/841
摘要： A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.
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公开(公告)号：US20240188307A1
公开(公告)日：2024-06-06
申请号：US18441204
申请日：2024-02-14
申请人： Kioxia Corporation
IPC分类号： H10B63/00 , H01L21/02 , H01L21/28 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L21/3213 , H01L21/762 , H01L27/105 , H01L29/51 , H10B43/27 , H10B43/30 , H10B43/35 , H10B43/40 , H10B69/00 , H10B99/00 , H10N70/00 , H10N70/20
CPC分类号： H10B63/845 , H01L21/02532 , H01L21/02595 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L29/40117 , H01L29/513 , H01L29/518 , H10B43/27 , H10B43/30 , H10B43/35 , H10B43/40 , H10B63/00 , H10B63/20 , H10B63/30 , H10B69/00 , H10B99/00 , H10N70/021 , H10N70/231 , H10N70/801 , H10N70/882 , H10N70/028 , H10N70/20 , H10N70/823 , H10N70/8413 , H10N70/8828 , H10N70/8833
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
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公开(公告)号：US20230413690A1
公开(公告)日：2023-12-21
申请号：US18242550
申请日：2023-09-06
发明人： Shih-Wei Su , Da-Jun Lin , Chih-Wei Chang , Bin-Siang Tsai , Ting-An Chien
CPC分类号： H10N70/063 , H10B63/00 , H10N70/028 , H10N70/041 , H10N70/841 , H10N70/8833
摘要： The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
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公开(公告)号：US12089512B2
公开(公告)日：2024-09-10
申请号：US18242550
申请日：2023-09-06
发明人： Shih-Wei Su , Da-Jun Lin , Chih-Wei Chang , Bin-Siang Tsai , Ting-An Chien
CPC分类号： H10N70/063 , H10B63/00 , H10N70/028 , H10N70/041 , H10N70/841 , H10N70/8833
摘要： The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
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公开(公告)号：US11937437B2
公开(公告)日：2024-03-19
申请号：US17381911
申请日：2021-07-21
申请人： Kioxia Corporation
IPC分类号： H10B63/00 , H01L21/02 , H01L21/28 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L21/3213 , H01L21/762 , H01L27/105 , H01L29/51 , H10B43/27 , H10B43/30 , H10B43/35 , H10B43/40 , H10B69/00 , H10B99/00 , H10N70/00 , H10N70/20
CPC分类号： H10B63/845 , H01L21/02532 , H01L21/02595 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L29/40117 , H01L29/513 , H01L29/518 , H10B43/27 , H10B43/30 , H10B43/35 , H10B43/40 , H10B63/00 , H10B63/20 , H10B63/30 , H10B69/00 , H10B99/00 , H10N70/021 , H10N70/231 , H10N70/801 , H10N70/882 , H10N70/028 , H10N70/20 , H10N70/823 , H10N70/8413 , H10N70/8828 , H10N70/8833
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
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公开(公告)号：US11793091B2
公开(公告)日：2023-10-17
申请号：US17114438
申请日：2020-12-07
发明人： Shih-Wei Su , Da-Jun Lin , Chih-Wei Chang , Bin-Siang Tsai , Ting-An Chien
CPC分类号： H10N70/063 , H10B63/00 , H10N70/028 , H10N70/041 , H10N70/841 , H10N70/8833
摘要： The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
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公开(公告)号：US11723292B2
公开(公告)日：2023-08-08
申请号：US16910609
申请日：2020-06-24
发明人： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
CPC分类号： H10N70/8265 , H10B63/30 , H10N70/011 , H10N70/063 , H10N70/066 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/021 , H10N70/023 , H10N70/026 , H10N70/028 , H10N70/041 , H10N70/043 , H10N70/046 , H10N70/061 , H10N70/068 , H10N70/231 , H10N70/235 , H10N70/245 , H10N70/25 , H10N70/253 , H10N70/257 , H10N70/801 , H10N70/821 , H10N70/823 , H10N70/828 , H10N70/8413 , H10N70/8416 , H10N70/8418 , H10N70/8613 , H10N70/8616 , H10N70/881 , H10N70/882 , H10N70/883 , H10N70/884 , H10N70/8822 , H10N70/8825 , H10N70/8828 , H10N70/8836 , H10N70/8845
摘要： The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
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公开(公告)号：US20230172079A1
公开(公告)日：2023-06-01
申请号：US17997447
申请日：2021-04-30
发明人： Michael KOZICKI , Ninad CHAMELE , Mehmet BALABAN
CPC分类号： H10N70/245 , H10N70/028 , H10N70/823 , H10N70/8416 , H10N70/8833
摘要： Lateral programmable metallization cells may comprise a solid electrolyte layer, an anode coupled to the solid electrolyte layer, and a cathode coupled to the solid electrolyte layer. Exemplary solid electrolyte layers may comprise a first layer comprising an oxide electrolyte and a copper species and a second layer comprising at least one copper species, the second layer coupled to the first layer.
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