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1.发明申请MEMS STRUCTURE WITH AN ETCH STOP LAYER BURIED WITHIN INTER-DIELECTRIC LAYER 审中-公开具有在电介质层内覆盖的蚀刻停止层的MEMS结构公开(公告)号：US20170036905A1
公开(公告)日：2017-02-09
申请号：US15295997
申请日：2016-10-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
CPC classification number: B81B3/0075 , B81B2207/07 , B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.
Abstract translation: MEMS结构包括衬底，在衬底的前侧上的介电层，介电层之间的MEMS组件，以及设置在介质间介质层内并通过衬底的室。 该腔室在衬底的背面具有开口。 蚀刻停止层设置在介电层内。 该室具有与开口相对的天花板和连接天花板的侧壁。 侧壁包括蚀刻停止层的一部分。
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Patent Agency Ranking
公开(公告)号：US10927000B2
公开(公告)日：2021-02-23
申请号：US15295997
申请日：2016-10-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.
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公开(公告)号：US08936960B1
公开(公告)日：2015-01-20
申请号：US13933135
申请日：2013-07-02
Applicant: United Microelectronics Corp.
Inventor： Kuan-Yu Wang , Hui-Min Wu , Kun-Che Hsieh
IPC: H01L21/00 , H01L21/4763 , H01L21/44 , B81C1/00
CPC classification number: B81B3/0072 , B81B2201/0235 , B81B2201/0242 , B81C2203/0742
Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
Abstract translation: 一种用于制造集成装置的方法包括以下步骤。 首先，在基板上形成多层结构，其中多层结构被嵌入在下隔离层中。 然后，在下隔离层的顶表面上形成底部导电图案和顶部导电图案，其中顶部导电图案位于底部导电图案的顶表面上。 之后，顶部导电图案的部分被去除以暴露底部导电图案的部分。 随后，上隔离层沉积在下隔离层上，使得上隔离层可以与底导电图案的部分直接接触。 最后，去除下隔离层和上隔离层的部分以露出基板的部分。
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4.发明授权Method for forming MEMS structure with an etch stop layer buried within inter-dielectric layer 有权用埋置在介电层内的蚀刻停止层形成MEMS结构的方法公开(公告)号：US09499399B2
公开(公告)日：2016-11-22
申请号：US13917655
申请日：2013-06-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
IPC: B81C1/00 , H01L21/302 , H01L21/461
CPC classification number: B81B3/0075 , B81B2207/07 , B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。
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公开(公告)号：US20150011035A1
公开(公告)日：2015-01-08
申请号：US13933135
申请日：2013-07-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuan-Yu Wang , Hui-Min Wu , Kun-Che Hsieh
IPC: B81C1/00
CPC classification number: B81B3/0072 , B81B2201/0235 , B81B2201/0242 , B81C2203/0742
Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
Abstract translation: 一种用于制造集成装置的方法包括以下步骤。 首先，在基板上形成多层结构，其中多层结构被嵌入在下隔离层中。 然后，在下隔离层的顶表面上形成底部导电图案和顶部导电图案，其中顶部导电图案位于底部导电图案的顶表面上。 之后，顶部导电图案的部分被去除以暴露底部导电图案的部分。 随后，上隔离层沉积在下隔离层上，使得上隔离层可以与底导电图案的部分直接接触。 最后，去除下隔离层和上隔离层的部分以露出基板的部分。
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公开(公告)号：US20140367805A1
公开(公告)日：2014-12-18
申请号：US13917655
申请日：2013-06-14
Applicant: United Microelectronics Corp.
Inventor： Li-Che Chen , Te-Yuan Wu , Chia-Huei Lin , Hui-Min Wu , Kun-Che Hsieh , Kuan-Yu Wang , Chung-Yi Chiu
IPC: B81C1/00
CPC classification number: B81B3/0075 , B81B2207/07 , B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。
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