公开(公告)号：US20180323227A1

公开(公告)日：2018-11-08

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L21/306 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US10580823B2

公开(公告)日：2020-03-03

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US09852912B1

公开(公告)日：2017-12-26

申请号：US15270638

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Liang Yi ,  Wen-Bo Ding ,  Chien-Kee Pang ,  Yu-Yang Chen

IPC: H01L21/4763 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L21/28273

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.