公开(公告)号：US20180323227A1

公开(公告)日：2018-11-08

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L21/306 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US12249607B2

公开(公告)日：2025-03-11

申请号：US18152781

申请日：2023-01-11

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US20230411343A1

公开(公告)日：2023-12-21

申请号：US17883595

申请日：2022-08-08

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Kai Zhu ,  Chien-Kee Pang ,  Chia-Liang Liao

IPC: H01L23/00 ,  H01L21/02

CPC classification number: H01L24/80 ,  H01L21/02337 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.

公开(公告)号：US20230154926A1

公开(公告)日：2023-05-18

申请号：US18152781

申请日：2023-01-11

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan QI ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L21/76256 ,  H01L21/02274

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US11456221B2

公开(公告)日：2022-09-27

申请号：US16906330

申请日：2020-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Chien-Kee Pang ,  Xin Zhao

IPC: H01L21/66

Abstract: A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.

公开(公告)号：US11605648B2

公开(公告)日：2023-03-14

申请号：US17383283

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US09780101B1

公开(公告)日：2017-10-03

申请号：US15361065

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Wenbo Ding ,  Xiaofei Han ,  Chien-Kee Pang ,  Yu-Yang Chen ,  Jubao Zhang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

公开(公告)号：US20230094739A1

公开(公告)日：2023-03-30

申请号：US17510392

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  Sheng Zhang ,  XINGXING CHEN ,  Chien-Kee Pang

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/16

Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

公开(公告)号：US20220415926A1

公开(公告)日：2022-12-29

申请号：US17383283

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US10580823B2

公开(公告)日：2020-03-03

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.