公开(公告)号：US20200373164A1

公开(公告)日：2020-11-26

申请号：US16417542

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEI XU ,  WENBO DING ,  Yu-Yang Chen ,  Wang Xiang

IPC: H01L21/28 ,  H01L27/11563 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

公开(公告)号：US09852912B1

公开(公告)日：2017-12-26

申请号：US15270638

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Liang Yi ,  Wen-Bo Ding ,  Chien-Kee Pang ,  Yu-Yang Chen

IPC: H01L21/4763 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L21/28273

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

公开(公告)号：US10916634B2

公开(公告)日：2021-02-09

申请号：US16417542

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Xu ,  Wenbo Ding ,  Yu-Yang Chen ,  Wang Xiang

IPC: H01L21/28 ,  H01L27/11563 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

公开(公告)号：US09780101B1

公开(公告)日：2017-10-03

申请号：US15361065

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Wenbo Ding ,  Xiaofei Han ,  Chien-Kee Pang ,  Yu-Yang Chen ,  Jubao Zhang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

公开(公告)号：US20140196251A1

公开(公告)日：2014-07-17

申请号：US13740254

申请日：2013-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： YINGJIE XU ,  Chaw Che ,  Yu-Yang Chen ,  Liang-Yong Tan ,  HAI YUAN ,  XIANYU MENG

IPC: H01L21/67

CPC classification number: H01L21/67017 ,  C23C16/4405

Abstract: A semiconductor fabricating apparatus includes a reaction chamber, a first gas pipeline, and a second gas pipeline. The first gas pipeline includes a first cleaning gas pipeline for providing a first cleansing gas to the reaction chamber in a cleansing process, and a second cleansing gas pipeline for providing a second cleansing gas to the reaction chamber in the cleansing process. The first cleansing gas pipeline and the second cleansing gas pipeline are connected in parallel. The second gas pipeline provides a reactive gas to the reaction chamber in a fabricating process. The first gas pipeline and the second gas pipeline are connected in parallel.

Abstract translation: 半导体制造装置包括反应室，第一气体管道和第二气体管道。 第一气体管道包括用于在清洁过程中向反应室提供第一清洁气体的第一清洁气体管道和用于在清洁过程中向反应室提供第二清洗气体的第二清洁气体管道。 第一清洁气体管道和第二清洁气体管道并联连接。 第二气体管道在制造过程中向反应室提供反应气体。 第一气体管道和第二气体管道并联连接。