公开(公告)号：US09929264B2

公开(公告)日：2018-03-27

申请号：US15628028

申请日：2017-06-20

Applicant: United Microelectronics Corporation

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L29/417 ,  H01L21/311 ,  H01L21/768 ,  H01L29/06 ,  H01L21/225

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

公开(公告)号：US09570315B2

公开(公告)日：2017-02-14

申请号：US14662142

申请日：2015-03-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chueh-Yang Liu ,  Yi-Liang Ye ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/02238 ,  H01L21/28238 ,  H01L21/823462 ,  H01L29/66545

Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).

Abstract translation: 界面氧化层形成的方法包括多个步骤。 步骤（S1）是从衬底的表面除去天然氧化物层; 步骤（S2）是通过比拉鱼溶液（SPM）在基板的表面上形成氧化物层; 步骤（S3）是通过标准清洁1（SC1）清洁氧化物层的表面，并且步骤（S4）通过包含稀释氟化氢（dHF）和臭氧化纯水（DIO3）的溶液蚀刻氧化物层 ）。

公开(公告)号：US09793105B1

公开(公告)日：2017-10-17

申请号：US15225829

申请日：2016-08-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chun-Wei Yu ,  Hsu Ting ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Kuang-Hsiu Chen ,  Yi-Liang Ye

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/02063 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6653

Abstract: The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and H2O2, and a second solution, consisting of dHF and DIO3; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO3, and a fourth solution, consisting of NH4OH and DIO3 before formation of the source/drain structure.

公开(公告)号：US09716165B1

公开(公告)日：2017-07-25

申请号：US15188194

申请日：2016-06-21

Applicant: United Microelectronics Corporation

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L23/48 ,  H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L21/225 ,  H01L21/311 ,  H01L21/768 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.