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公开(公告)号:US10608106B2
公开(公告)日:2020-03-31
申请号:US15955706
申请日:2018-04-18
Inventor: Ming Qiao , Zhengkang Wang , Ruidi Wang , Zhao Qi , Bo Zhang
Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.
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公开(公告)号:US10720524B1
公开(公告)日:2020-07-21
申请号:US16536333
申请日:2019-08-09
Inventor: Ming Qiao , Zhengkang Wang , Dong Fang , Ruidi Wang , Bo Zhang
IPC: H01L29/78 , H01L29/40 , H01L29/423 , H01L29/66
Abstract: A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.
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