公开(公告)号：US20190228517A1

公开(公告)日：2019-07-25

申请号：US16370136

申请日：2019-03-29

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Yuhua CHENG ,  Chun YIN ,  Haonan ZHANG ,  Xuegang HUANG ,  Ting XUE ,  Kai CHEN ,  Yi LI

IPC: G06T7/00 ,  G06T7/136 ,  G06K9/34

Abstract: The present invention provides a method for separating out a defect image from a thermogram sequence based on feature extraction and multi-objective optimization, we find that different kinds of TTRs have big differences in some physical quantities, such as the energy, temperature change rate during endothermic process, temperature change rate during endothermic process, average temperature, maximum temperature. The present invention extract these features (physical quantities) and cluster the selected TTRs into L clusters based on their feature vectors, which deeply digs the physical meanings contained in each TTR, makes the clustering more rational, and improves the accuracy of defect separation. Meanwhile, the present invention creates a multi-objective function to select a RTTR for each cluster based on multi-objective optimization. The multi-objective function does not only fully consider the similarities between the RTTR and other TTRs in the same cluster, but also considers the dissimilarities between the RTTR and the TTRs in other clusters, the RTTR is more representative, which guarantees the accuracy of describing the defect outline.

公开(公告)号：US20210074699A1

公开(公告)日：2021-03-11

申请号：US16839089

申请日：2020-04-03

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Linrong HE ,  Yi LI ,  Chunlan LAI ,  Bo Zhang

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739

Abstract: An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.