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    HTO offset for long Leffective, better device performance
    3.
    发明授权
    HTO offset for long Leffective, better device performance 有权
    HTO偏移长期有效，设备性能更好

    公开(公告)号：US08653581B2

    公开(公告)日：2014-02-18

    申请号：US12342016

    申请日：2008-12-22

    申请人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    发明人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    IPC分类号： H01L27/115

    CPC分类号： H01L29/792 ,  G11C16/3427 ,  H01L21/26586 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/66833 ,  H01L29/7923

    摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

    摘要翻译： 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

    HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
    4.
    发明申请
    HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE 有权
    HTO OFFSET为长期的，更好的设备性能

    公开(公告)号：US20140167138A1

    公开(公告)日：2014-06-19

    申请号：US14109157

    申请日：2013-12-17

    申请人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    发明人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    IPC分类号： H01L29/792 ,  H01L29/66

    CPC分类号： H01L29/792 ,  G11C16/3427 ,  H01L21/26586 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/66833 ,  H01L29/7923

    摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

    摘要翻译： 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

    HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
    5.
    发明申请
    HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE 有权
    HTO OFFSET为长期的，更好的设备性能

    公开(公告)号：US20100155817A1

    公开(公告)日：2010-06-24

    申请号：US12342016

    申请日：2008-12-22

    申请人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    发明人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    IPC分类号： H01L21/265 ,  H01L29/792

    CPC分类号： H01L29/792 ,  G11C16/3427 ,  H01L21/26586 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/66833 ,  H01L29/7923

    摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

    摘要翻译： 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

    HTO offset and BL trench process for memory device to improve device performance
    8.
    发明授权
    HTO offset and BL trench process for memory device to improve device performance 有权
    HTO偏移和BL沟槽工艺为存储器件提高器件性能

    公开(公告)号：US08330209B2

    公开(公告)日：2012-12-11

    申请号：US13069710

    申请日：2011-03-23

    申请人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi

    发明人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/66833 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7923

    摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

    摘要翻译： 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。