公开(公告)号：US07785965B2

公开(公告)日：2010-08-31

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US20080064165A1

公开(公告)日：2008-03-13

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07767517B2

公开(公告)日：2010-08-03

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US20080149999A1

公开(公告)日：2008-06-26

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07696038B1

公开(公告)日：2010-04-13

申请号：US11412365

申请日：2006-04-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  G11C16/3418 ,  G11C16/3427

摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

摘要翻译： 提供了制造闪速存储器件的方法。 根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。 在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。 第一杂质掺杂区域形成在沟槽下面的衬底内。

公开(公告)号：US20050164450A1

公开(公告)日：2005-07-28

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/74 ,  H01L29/417 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US07301193B2

公开(公告)日：2007-11-27

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US06524914B1

公开(公告)日：2003-02-25

申请号：US09699972

申请日：2000-10-30

申请人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

发明人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.

摘要翻译： 本发明的一个方面涉及一种制造闪存单元的方法，所述闪存单元包括以下步骤：提供其上具有闪存单元的基板; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 清洗基材; 以及植入第二类型的介质剂量漏极注入以在所述衬底中邻近所述闪存单元形成源极区域和漏极区域。

公开(公告)号：US06653189B1

公开(公告)日：2003-11-25

申请号：US09699711

申请日：2000-10-30

申请人： Sameer Haddad ,  Yue-song He ,  Timothy Thurgate ,  Chi Chang ,  Mark W. Randolph ,  Ngaching Wong

发明人： Sameer Haddad ,  Yue-song He ,  Timothy Thurgate ,  Chi Chang ,  Mark W. Randolph ,  Ngaching Wong

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.

摘要翻译： 本发明的一个方面涉及一种制造闪存单元的方法，包括以下步骤：在其上提供闪存单元; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 在衬底上形成MDD掩模，MDD掩模覆盖源极线并具有对应于漏极线的开口; 以及植入第二类型的介质剂量漏极注入，以在与所述闪存单元相邻的所述衬底中形成漏极区域。