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    Low-latency shared memory channel across address spaces without system call overhead in a computing system
    3.
    发明授权
    Low-latency shared memory channel across address spaces without system call overhead in a computing system 有权

    公开(公告)号：US11249660B2

    公开(公告)日：2022-02-15

    申请号：US17012411

    申请日：2020-09-04

    Applicant: VMWARE, INC.

    Inventor： Mounesh Badiger ,  Wenguang Wang ,  Adrian Drzewiecki

    IPC: G06F3/06 ,  G06F12/10 ,  G06F9/455 ,  G06F12/06 ,  G06F21/44 ,  G06F16/172

    Abstract: Examples provide a method of communication between a client application and a filesystem server in a virtualized computing system. The client application executes in a virtual machine (VM) and the filesystem server executes in a hypervisor. The method includes: allocating, by the client application, first shared memory in a guest virtual address space of the client application; creating a guest application shared memory channel between the client application and the filesystem server upon request by the client application to a driver in the VM, the driver in communication with the filesystem server, the guest application shared memory channel using the first shared memory; sending authentication information associated with the client application to the filesystem server to create cached authentication information at the filesystem server; and submitting a command in the guest application shared memory channel from the client application to the filesystem server, the command including the authentication information.

    Secure Cross-Process Memory Sharing
    5.
    发明申请
    Secure Cross-Process Memory Sharing 有权
    安全的跨进程内存共享

    公开(公告)号：US20160306578A1

    公开(公告)日：2016-10-20

    申请号：US14686527

    申请日：2015-04-14

    Applicant: VMware, Inc.

    Inventor： Adrian Drzewiecki ,  Christoph Klee ,  Mounesh Badiger

    IPC: G06F3/06

    CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/14 ,  G06F12/1416 ,  G06F13/1663

    Abstract: Techniques for enabling secure cross-process memory sharing are provided. In one set of embodiments, a first user process executing on a computer system can create a memory handle representing a memory space of the first user process. The first user process can further define one or more access restrictions with respect to the memory handle. The first user process can then transmit the memory handle to a second user process executing on the computer system, the memory handle enabling the second user process to access at least a portion of the first process' memory space, subject to the one or more access restrictions.

    Abstract translation: 提供了用于实现安全的跨进程内存共享的技术。 在一组实施例中，在计算机系统上执行的第一用户进程可以创建表示第一用户进程的存储器空间的存储器句柄。 第一用户进程可以进一步定义关于存储器句柄的一个或多个访问限制。 然后，第一用户进程可以将存储器句柄传送到在计算机系统上执行的第二用户进程，存储器句柄使得第二用户进程能够访问第一进程的存储器空间的至少一部分，受到一个或多个访问 限制

    Secure cross-process memory sharing
    8.
    发明授权
    Secure cross-process memory sharing 有权
    安全的跨进程内存共享

    公开(公告)号：US09542112B2

    公开(公告)日：2017-01-10

    申请号：US14686527

    申请日：2015-04-14

    Applicant: VMware, Inc.

    Inventor： Adrian Drzewiecki ,  Christoph Klee ,  Mounesh Badiger

    IPC: G06F12/14 ,  G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/14 ,  G06F12/1416 ,  G06F13/1663

    Abstract: Techniques for enabling secure cross-process memory sharing are provided. In one set of embodiments, a first user process executing on a computer system can create a memory handle representing a memory space of the first user process. The first user process can further define one or more access restrictions with respect to the memory handle. The first user process can then transmit the memory handle to a second user process executing on the computer system, the memory handle enabling the second user process to access at least a portion of the first process' memory space, subject to the one or more access restrictions.

    Abstract translation: 提供了用于实现安全的跨进程内存共享的技术。 在一组实施例中，在计算机系统上执行的第一用户进程可以创建表示第一用户进程的存储器空间的存储器句柄。 第一用户进程可以进一步定义关于存储器句柄的一个或多个访问限制。 然后，第一用户进程可以将存储器句柄传送到在计算机系统上执行的第二用户进程，存储器句柄使得第二用户进程能够访问第一进程的存储器空间的至少一部分，受到一个或多个访问 限制

    Low-latency shared memory channel across address spaces in a computing system
    9.
    发明授权
    Low-latency shared memory channel across address spaces in a computing system 有权

    公开(公告)号：US11513832B2

    公开(公告)日：2022-11-29

    申请号：US17013727

    申请日：2020-09-07

    Applicant: VMWARE, INC.

    Inventor： Mounesh Badiger ,  Wenguang Wang ,  Adrian Drzewiecki ,  Maxime Austruy ,  Satish Pudi

    IPC: G06F9/455 ,  G06F12/1036 ,  G06F12/02

    Abstract: Examples provide a method of communication between a client driver and a filesystem server. The client driver executes in a virtual machine (VM) and the filesystem server executes in a hypervisor. The method includes: allocating, by the client driver, shared memory in an address space of the VM for the communication; sending identification information for the shared memory from the client driver to the filesystem server through an inter-process communication channel between the client driver and the filesystem server; identifying, by the filesystem server in cooperation with a kernel of the hypervisor, the shared memory within an address space of the hypervisor, based on the identification information, to create a shared memory channel; sending commands from the client driver to the filesystem server through the shared memory channel; and receiving completion messages for the commands from the filesystem server to the client driver through the shared memory channel.

    System and method of a highly concurrent cache replacement algorithm
    10.
    发明授权
    System and method of a highly concurrent cache replacement algorithm 有权

    公开(公告)号：US11086779B2

    公开(公告)日：2021-08-10

    申请号：US16679570

    申请日：2019-11-11

    Applicant: VMware, Inc.

    Inventor： Wenguang Wang ,  Mounesh Badiger ,  Abhay Kumar Jain ,  Junlong Gao ,  Zhaohui Guo ,  Richard P. Spillane

    IPC: G06F12/08 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/14 ,  G06F12/1018 ,  G06F12/0871

    Abstract: Disclosed are a method and system for managing multi-threaded concurrent access to a cache data structure. The cache data structure includes a hash table and three queues. The hash table includes a list of elements for each hash bucket with each hash bucket containing a mutex object and elements in each of the queues containing lock objects. Multiple threads can each lock a different hash bucket to have access to the list, and multiple threads can each lock a different element in the queues. The locks permit highly concurrent access to the cache data structure without conflict. Also, atomic operations are used to obtain pointers to elements in the queues so that a thread can safely advance each pointer. Race conditions that are encountered with locking an element in the queues or entering an element into the hash table are detected, and the operation encountering the race condition is retried.

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