公开(公告)号：US06317000B1

公开(公告)日：2001-11-13

申请号：US09765485

申请日：2001-01-18

申请人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

发明人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

IPC分类号： H03F345

CPC分类号： H03F1/523 ,  H03F3/3016

摘要： An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (VDD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (VSS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor. A first overload recovery circuit (X) is coupled between the output conductor (22) and the gate of the pull-up transistor for limiting the voltage on the gate of the pull-up transistor in response to the output voltage (Vout) when the output voltage is within a first predetermined range of the first supply voltage (VDD). A second overload recovery circuit (Y) is coupled between the output conductor (22) and the gate of the pull-down transistor for limiting the voltage on the gate of the pull-down transistor in response to the output voltage (Vout) when the output voltage is within a second predetermined range of the second supply voltage (VSS).

摘要翻译： 运算放大器包括接收输入信号（Vin）并具有第一（14）和第二（16）输出端的输入级（13），并且还包括具有上拉晶体管（M11）的输出级（10）和 一个下拉晶体管（M2）。 上拉晶体管具有耦合到第一电源电压（VDD）的源极，耦合到第一输出端子（14）的栅极以及耦合到导通输出信号（Vout）的输出导体（22）的漏极。 下拉晶体管（M2）具有耦合到第二电源电压（VSS）的源极，耦合到第二输出端子（16）的栅极和耦合到输出导体（22）的漏极。 AB控制电路（20）耦合在上拉晶体管的栅极和下拉晶体管之间。 第一过载恢复电路（X）耦合在输出导体（22）和上拉晶体管的栅极之间，用于响应于输出电压（Vout）来限制上拉晶体管的栅极上的电压 输出电压在第一电源电压（VDD）的第一预定范围内。 第二过载恢复电路（Y）耦合在输出导体（22）和下拉晶体管的栅极之间，用于响应于输出电压（Vout）来限制下拉晶体管的栅极上的电压， 输出电压在第二电源电压（VSS）的第二预定范围内。

公开(公告)号：US06703900B2

公开(公告)日：2004-03-09

申请号：US10163113

申请日：2002-06-05

申请人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

发明人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

IPC分类号： H03F152

CPC分类号： H03F3/3028 ,  H03F1/308 ,  H03F1/3217

摘要： A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.

摘要翻译： 差分放大器包括输入级（13）和输出级（100），输出级（100）包括具有耦合到电源电压（VDD）的源极的输出晶体管（M11），耦合到输入级的端子（14）的栅极， 以及耦合到输出导体（22）的漏极。 恢复电路（1A）耦合在电源电压和输出晶体管的栅极之间，用于响应于输出电压在电源电压的预定范围内来限制输出晶体管的栅极上的电压，并且包括恢复晶体管 （M4），其源极耦合到所述输出导体，以及耦合到所述输出晶体管的栅极的漏极和具有内置偏移的共栅极放大器（29A），所述第一输入耦合到所述输出导体，第二输入耦合 并且耦合到恢复晶体管的栅极的输出。

公开(公告)号：US06359512B1

公开(公告)日：2002-03-19

申请号：US09765267

申请日：2001-01-18

申请人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

发明人： Vadim V. Ivanov ,  Shilong Zhang ,  Gregory H. Johnson

IPC分类号： H03F345

CPC分类号： H03F3/45183 ,  H03F1/3223 ,  H03F1/483 ,  H03F3/303 ,  H03F3/45192 ,  H03F2203/45682 ,  H03F2203/45702

摘要： An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32). If the differential input signal is of a first polarity and is of a magnitude substantially greater than a threshold voltage of the first unbalanced differential amplifier (31), the magnitude of a turn-on voltage of the pull-down transistor (M12) is decreased and the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased in response to an output voltage produced by the first unbalanced differential amplifier (31). However, if the differential input signal is of a second polarity and is of a magnitude substantially greater than a threshold voltage of the second unbalanced differential amplifier (32), then the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased and the magnitude of a turn-on voltage of the pull-down transistor (M12) is simultaneously decreased, in response to an output voltage produced by the second unbalanced differential amplifier (32).

摘要翻译： 运算放大器包括具有第一（2）和第二（3）输入导体的差分输入级（30），耦合到差分输入级（30）的输出的AB类输出级（20）并且包括上拉 晶体管（M11）具有耦合到第一电源电压（VDD）的源极，耦合到输出导体（17）的漏极和耦合到AB类控制电路（11）的第一端子（14）的栅极，以及 具有耦合到第二电源电压（GND）的源极的下拉晶体管（M12），耦合到输出导体（17）的漏极和耦合到AB类控制电路的第二端子（15）的栅极 11）。 差分输入信号施加在第一（2）和第二（3）输入导体之间，同时也被施加在第一不平衡差分放大器（31）的第一和第二输入端之间以及在第二和第二输入端之间的第二和第二输入端 放大器（32）。 如果差分输入信号具有第一极性并且具有显着大于第一不平衡差分放大器（31）的阈值电压的幅度，则下拉晶体管（M12）的接通电压的幅度减小 并且上拉晶体管（M11）的接通电压的大小响应于由第一不平衡差分放大器（31）产生的输出电压而增加。 然而，如果差分输入信号具有第二极性并且具有显着大于第二不平衡差分放大器（32）的阈值电压的幅度，则上拉晶体管（M11）的接通电压的幅度 ）并且响应于由第二不平衡差分放大器（32）产生的输出电压同时降低下拉晶体管（M12）的接通电压的幅度。

公开(公告)号：US06545538B1

公开(公告)日：2003-04-08

申请号：US09677967

申请日：2000-10-03

申请人： Vadim V. Ivanov ,  Gregory H. Johnson ,  Stephen J. Sanchez

发明人： Vadim V. Ivanov ,  Gregory H. Johnson ,  Stephen J. Sanchez

IPC分类号： H03F345

CPC分类号： H03F3/45192 ,  H03F3/303 ,  H03F2203/30015 ,  H03F2203/30063 ,  H03F2203/45318

摘要： A rail-to-rail class AB output stage includes a P-channel pull-up transistor (4) having a source coupled to a first supply rail voltage (V+), a gate coupled to a first input conductor (2) of the output stage, and a drain coupled to an output terminal (6) of the output stage. An N-channel pull-down transistor (5) includes a source coupled to a second supply rail voltage (GROUND), a gate coupled to a second input conductor (3) of the output stage, and a drain coupled to the output terminal (6). A P-channel first bias transistor (20) includes a source coupled to the first input conductor (2) and a drain coupled to the second input terminal (3). A first bias circuit coupled between the first and second supply rail voltages produces a first bias voltage (21) on a gate of the first bias transistor (20). A P-channel second bias transistor (10) includes a source coupled to be first input conductor (2). An N-channel third bias transistor (11) includes a source coupled to the second input terminal (3) and a drain connected to a drain of the second bias transistor (10) and to a non-inverting input of a servo amplifier (12) having an output coupled to a gate of the second bias transistor (10) and an inverting input coupled to a gate of the third bias transistor (11) or a suitable reference voltage. A second bias circuit coupled between the first and second supply rail voltages produces a second bias voltage (16) on the gate of the third bias transistor (11) and the inverting input of the servo amplifier.

摘要翻译： 轨到轨AB类输出级包括具有耦合到第一电源电压（V +）的源极的P沟道上拉晶体管（4），耦合到输出的第一输入导体（2）的栅极 级和与所述输出级的输出端（6）耦合的漏极。 N沟道下拉晶体管（5）包括耦合到第二电源轨电压（GROUND）的源极，耦合到输出级的第二输入导体（3）的栅极和耦合到输出端子 6）。 P沟道第一偏置晶体管（20）包括耦合到第一输入导体（2）的源极和耦合到第二输入端子（3）的漏极。 耦合在第一和第二电源轨电压之间的第一偏置电路在第一偏置晶体管（20）的栅极上产生第一偏置电压（21）。 P沟道第二偏置晶体管（10）包括耦合到第一输入导体（2）的源极。 N沟道第三偏置晶体管（11）包括耦合到第二输入端（3）的源极和连接到第二偏置晶体管（10）的漏极的漏极和伺服放大器（12）的非反相输入端 ）具有耦合到第二偏置晶体管（10）的栅极的输出端和耦合到第三偏置晶体管（11）的栅极的反相输入端或合适的参考电压。 耦合在第一和第二电源轨电压之间的第二偏置电路在第三偏置晶体管（11）的栅极和伺服放大器的反相输入端产生第二偏置电压（16）。

公开(公告)号：US06356153B1

公开(公告)日：2002-03-12

申请号：US09717186

申请日：2000-11-20

申请人： Vadim V. Ivanov ,  Gregory H. Johnson

发明人： Vadim V. Ivanov ,  Gregory H. Johnson

IPC分类号： H03F345

CPC分类号： H03F3/3028 ,  H03F3/303 ,  H03F3/45219 ,  H03F3/45529 ,  H03F3/45677 ,  H03F2203/45292 ,  H03F2203/45398

摘要： A rail-to-rail differential amplifier includes first and second input terminals, and an output terminal and an input stage including differentially connected N-channel first and second input transistors, and differentially connected P-channel third and fourth input transistors. A P-channel first cascode transistor has a source coupled to a first supply voltage to the drain of the first input transistor. An N-channel cascode transistor has a source coupled by a second resistive element to a second supply voltage and to the drain of the third input transistor. A first gain boost amplifier has an output coupled to a gate of the first cascode transistor, a first input coupled to the source of the first cascode transistor and the drain of the first input transistor, and a second input coupled to a drain of the second input transistor and a bias control circuit. A second gain boost amplifier has an output coupled to a gate of the second cascode transistor, a first input coupled to the source of the second cascode transistor and to the drain of the third input transistor, and a second input coupled to a drain of the fourth input transistor and the bias control circuit. An output stage includes a pull-up transistor coupled between the first supply voltage and the output terminal, a pull-down transistor coupled between the second supply voltage and the output terminal, and a class AB bias circuit coupled between drain electrodes of the fist and second cascode transistors and between gate electrodes of the pull-up and pull-down transistors.

摘要翻译： 轨到轨差分放大器包括第一和第二输入端，以及包括差分连接的N沟道第一和第二输入晶体管以及差分连接的P沟道第三和第四输入晶体管的输出端和输入级。 P沟道第一共源共栅晶体管具有耦合到第一输入晶体管的漏极的第一电源电压的源极。 N沟道共源共栅晶体管具有由第二电阻元件耦合到第二电源电压的源极和与第三输入晶体管的漏极耦合的源极。 第一增益升压放大器具有耦合到第一共源共栅晶体管的栅极的输出，耦合到第一共源共栅晶体管的源极和第一输入晶体管的漏极的第一输入端以及耦合到第二共源共栅晶体管的漏极的第二输入端 输入晶体管和偏置控制电路。 第二增益升压放大器具有耦合到第二共源共栅晶体管的栅极的输出，耦合到第二共源共栅晶体管的源极和第三输入晶体管的漏极的第一输入端以及耦合到第二共源共栅晶体管的漏极的第二输入端 第四输入晶体管和偏置控制电路。 输出级包括耦合在第一电源电压和输出端子之间的上拉晶体管，耦合在第二电源电压和输出端子之间的下拉晶体管，以及耦合在第一电源电压和输出端子的漏电极之间的AB类偏置电路，以及 第二共源共栅晶体管和上拉和下拉晶体管的栅电极之间。

公开(公告)号：USD366039S

公开(公告)日：1996-01-09

申请号：US20931

申请日：1994-04-05

申请人： John A. Bailey ,  Glenn A. Bloomer ,  Gregory H. Johnson ,  Nicholas A. Brawne ,  Mark J. Ciesko ,  Donald J. Staufenberg

设计人： John A. Bailey ,  Glenn A. Bloomer ,  Gregory H. Johnson ,  Nicholas A. Brawne ,  Mark J. Ciesko ,  Donald J. Staufenberg

公开(公告)号：USD365814S

公开(公告)日：1996-01-02

申请号：US20922

申请日：1994-04-05

申请人： John A. Bailey ,  Glenn A. Bloomer ,  Gregory H. Johnson ,  Donald J. Staufenberg

设计人： John A. Bailey ,  Glenn A. Bloomer ,  Gregory H. Johnson ,  Donald J. Staufenberg

公开(公告)号：USD364614S

公开(公告)日：1995-11-28

申请号：US20909

申请日：1994-04-05

申请人： John A. Bailey ,  Glenn A. Bloomer ,  Gregory H. Johnson ,  Mark J. Ciesko ,  Donald J. Staufenberg

设计人： John A. Bailey ,  Glenn A. Bloomer ,  Gregory H. Johnson ,  Mark J. Ciesko ,  Donald J. Staufenberg

公开(公告)号：US07548418B2

公开(公告)日：2009-06-16

申请号：US11502254

申请日：2006-08-09

申请人： Robert C. Martin ,  Gregory H. Johnson ,  G. Phillip Rambosek ,  Leo W. Spychalla

发明人： Robert C. Martin ,  Gregory H. Johnson ,  G. Phillip Rambosek ,  Leo W. Spychalla

IPC分类号： G06F1/16

CPC分类号： G11B33/122 ,  G11B25/043

摘要： A data storage cartridge includes housing, a hard drive, and a connection assembly. The hard drive is stored within the housing and includes a non-tape storage medium and an electrical data connector configured to provide access to the non-tape storage medium. The electrical data connector includes a first number of connection terminals. The connection assembly is positioned within the housing and is coupled with each of the connection terminals of the electrical data connector. The connection assembly includes a second number of electrical targets spaced from and in electrical communication with the electrical data connector wherein the first number is greater than the second number. The electrical targets provide an interface for externally accessing the storage medium via the connection assembly and the electrical data connector.

摘要翻译： 数据存储盒包括壳体，硬盘驱动器和连接组件。 硬盘驱动器存储在壳体内，并且包括非磁带存储介质和被配置为提供对非磁带存储介质的访问的电数据连接器。 电气数据连接器包括第一数量的连接端子。 连接组件位于壳体内并且与电数据连接器的每个连接端子相连。 连接组件包括与电数据连接器隔开并与电数据连接器电通信的第二数量的电目标，其中第一数量大于第二数量。 电目标提供了用于经由连接组件和电数据连接器从外部访问存储介质的接口。

公开(公告)号：US06386471B1

公开(公告)日：2002-05-14

申请号：US09716743

申请日：2000-11-20

申请人： Joseph P. Keller ,  Gregg C. Hagen ,  Gregory D. Roberts ,  Gregory H. Johnson ,  Michael W. Johnson ,  Bryan W. Noble

发明人： Joseph P. Keller ,  Gregg C. Hagen ,  Gregory D. Roberts ,  Gregory H. Johnson ,  Michael W. Johnson ,  Bryan W. Noble

IPC分类号： G11B2304

CPC分类号： G11B23/107 ,  G11B23/113 ,  Y10T403/4991

摘要： System for releasably retaining portions of a data cartridge shell in an assembled configuration including at least one first boss tower on a first portion of the data cartridge shell having a receiving hole with an inner surface. At least one second boss tower on a second portion of the data cartridge shell including an outer surface is adapted to releasably engage with the receiving hole at a boss tower interface in the assembled configuration. A plurality of retention ribs and a plurality of guide ribs are located at the boss tower interface to releasably retain the first portion of the cartridge shell to the second portion.

摘要翻译： 用于将数据盒壳体的部分可释放地保持在组装构造中的系统，包括在数据盒壳体的第一部分上的至少一个第一凸起塔架，其具有带有内表面的接收孔。 在包括外表面的数据盒壳的第二部分上的至少一个第二凸台塔适于在组装的构型中在凸台塔接口处可释放地与接收孔接合。 多个保持肋和多个引导肋位于凸台塔界面处以可释放地将盒壳的第一部分保持在第二部分上。