公开(公告)号：US06114259A

公开(公告)日：2000-09-05

申请号：US362645

申请日：1999-07-27

申请人： Valeriy Sukharev ,  Warren Uesato ,  John Rongxiang Hu ,  Wei-Jen Hsia ,  Linggian Qian

发明人： Valeriy Sukharev ,  Warren Uesato ,  John Rongxiang Hu ,  Wei-Jen Hsia ,  Linggian Qian

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31138 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.

摘要翻译： 描述了一种用于处理低k碳掺杂的氧化硅介电材料的暴露表面以便保护低k碳掺杂的氧化硅介电材料在去除光致抗蚀剂掩模材料期间的损坏的方法。 该方法包括（a）首先用等离子体处理低k碳掺杂的氧化硅介电材料的暴露表面，所述等离子体能够在低k碳掺杂的氧化硅介电材料的暴露表面上及其附近形成致密层，并且（b）然后 用能够从半导体晶片去除光致抗蚀剂材料的温和氧化剂处理半导体晶片。 在低k碳掺杂的氧化硅电介质材料中形成通孔或接触开口之后，这些步骤将防止在去除蚀刻掩模期间低k碳掺杂的氧化硅介电材料的暴露表面的劣化。

公开(公告)号：US6166422A

公开(公告)日：2000-12-26

申请号：US79413

申请日：1998-05-13

申请人： Linggian Qian ,  Wen-Chin Stanley Yeh

发明人： Linggian Qian ,  Wen-Chin Stanley Yeh

IPC分类号： H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L29/00

CPC分类号： H01F41/046 ,  H01F17/0033 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is provided with an inductor formed therein which comprises a metal coil on an insulated surface over a semiconductor substrate, and a high magnetic susceptibility cobalt/nickel metal core located adjacent said metal coil, but spaced therefrom by one or more insulation layers. In one embodiment, the high magnetic susceptibility cobalt/nickel metal core is placed between lower and upper portions of the metal coil which are interconnected together by filled vias. In another embodiment, the metal coil is formed in a serpentine shape in one plane on an insulated surface over the semiconductor substrate, and the high magnetic susceptibility cobalt/nickel metal core is formed over the serpentine coil, but spaced from the serpentine coil by another insulation layer.

摘要翻译： 集成电路结构设置有形成在其中的电感器，其包括位于半导体衬底上的绝缘表面上的金属线圈和位于所述金属线圈附近的高磁化率钴/镍金属芯，但是通过一个或多个绝缘层与其隔开 。 在一个实施例中，高磁化率钴/镍金属芯放置在金属线圈的下部和上部之间，其通过填充的通孔互连在一起。 在另一个实施例中，金属线圈在半导体衬底上的绝缘表面上的一个平面中以蛇形形式形成，并且高磁化率钴/镍金属芯形成在蛇形线圈上，但是与蛇形线圈间隔开另一个 绝缘层。