公开(公告)号：US09356188B2

公开(公告)日：2016-05-31

申请号：US14480175

申请日：2014-09-08

Applicant: Veeco Instruments, Inc.

Inventor： Ajit Paranjpe ,  Jia Lee ,  Craig Metzner

IPC: H01L33/30 ,  H01L33/00 ,  H01L33/22

CPC classification number: H01L33/0079 ,  H01L33/22

Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.

Abstract translation: 将应力层施加到半导体叠层，以便以预定深度分离半导体叠层。 将拉伸力施加到应力层上，在预定深度压裂半导体叠层，并允许半导体叠层的所得上部用于制造半导体最终产品（例如，发光二极管）。 所产生的半导体堆叠的下部可以重新用于在其上生长新的半导体叠层。

公开(公告)号：US20150069420A1

公开(公告)日：2015-03-12

申请号：US14480175

申请日：2014-09-08

Applicant: Veeco Instruments, Inc.

Inventor： Ajit Paranjpe ,  Jia Lee ,  Craig Metzner

IPC: H01L33/30 ,  H01L33/00 ,  H01L33/04

CPC classification number: H01L33/0079 ,  H01L33/22

Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.

Abstract translation: 将应力层施加到半导体叠层，以便以预定深度分离半导体叠层。 将拉伸力施加到应力层上，在预定深度压裂半导体叠层，并允许半导体叠层的所得上部用于制造半导体最终产品（例如，发光二极管）。 所产生的半导体堆叠的下部可以重新用于在其上生长新的半导体叠层。

公开(公告)号：US20150187888A1

公开(公告)日：2015-07-02

申请号：US14585426

申请日：2014-12-30

Applicant: VEECO INSTRUMENTS, INC.

Inventor： Ajit Paranjpe ,  Craig Metzner ,  Joe Lamb

IPC: H01L29/20 ,  H01L21/683 ,  H01L33/12 ,  H01L33/00 ,  H01L33/32 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L33/0075 ,  H01L33/0079 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.

Abstract translation: 可以采用剥落工艺来在诸如体GaN衬底的高质量结晶氮化物衬底内的预定深度处产生断裂。 第一结晶导电膜层可以沿着断裂线从结晶氮化物衬底分离，并随后结合到包括传统低成本衬底的层叠堆叠。 如果第一结晶导电膜层的剥离表面在所得到的结构中暴露，则该结构可以用作可以生长高质量GaN基器件的衬底。

公开(公告)号：US09761671B2

公开(公告)日：2017-09-12

申请号：US14585426

申请日：2014-12-30

Applicant: Veeco Instruments, Inc.

Inventor： Ajit Paranjpe ,  Craig Metzner ,  Joe Lamb

IPC: H01L21/18 ,  H01L21/304 ,  H01L21/683 ,  H01L29/20 ,  H01L33/00

CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L33/0075 ,  H01L33/0079 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.