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公开(公告)号：US09938621B2
公开(公告)日：2018-04-10
申请号：US15151845
申请日：2016-05-11
Applicant: Veeco Instruments Inc.
Inventor： Bojan Mitrovic , Guanghua Wei , Eric A. Armour , Ajit Paranjpe
IPC: C23C16/455 , C23C16/458 , H01L21/687 , C30B25/16 , C30B29/06 , C23C16/46 , H01L21/02
CPC classification number: C23C16/4585 , C23C16/45504 , C23C16/45508 , C23C16/45591 , C23C16/4584 , C23C16/46 , C30B25/165 , C30B29/06 , H01L21/0254 , H01L21/0262 , H01L21/68735 , H01L21/68764 , H01L21/68771 , H01L21/68785
Abstract: Methods are provided for treating wafers using a wafer carrier rotated about an axis. The wafer carrier is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
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公开(公告)号：US20160251758A1
公开(公告)日：2016-09-01
申请号：US15151845
申请日：2016-05-11
Applicant: Veeco Instruments Inc.
Inventor： Bojan Mitrovic , Guanghua Wei , Eric A. Armour , Ajit Paranjpe
IPC: C23C16/458 , H01L21/687 , H01L21/02 , C23C16/455 , C23C16/46
CPC classification number: C23C16/4585 , C23C16/45504 , C23C16/45508 , C23C16/45591 , C23C16/4584 , C23C16/46 , C30B25/165 , C30B29/06 , H01L21/0254 , H01L21/0262 , H01L21/68735 , H01L21/68764 , H01L21/68771 , H01L21/68785
Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
Abstract translation: 使用绕轴旋转的晶片载体处理晶片的装置在操作期间设置有围绕晶片载体的环。 引导到载体的顶表面上的处理气体向外离开载体上方的轴并且越过环，并且在环的下游向下游。 向外流动的气体在载体和环上形成边界。 该环有助于在载体上保持基本均匀厚度的边界层，这促进了晶片的均匀处理。
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公开(公告)号：US20140326186A1
公开(公告)日：2014-11-06
申请号：US14332583
申请日：2014-07-16
Applicant: Veeco Instruments, Inc.
Inventor： Ajit Paranjpe , Alexander Gurary , William Quinn
Abstract: A VPE reactor is improved by providing temperature control to within 0.5° C., and greater process gas uniformity via novel reactor shaping, unique wafer motion structures, improvements in thermal control systems, improvements in gas flow structures, improved methods for application of gas and temperature, and improved control systems for detecting and reducing process variation.
Abstract translation: 通过提供温度控制在0.5℃以内，通过新型的反应器成型，独特的晶片运动结构，热控制系统的改进，气流结构的改进，改进的气体应用方法和 温度和改进的控制系统，用于检测和减少过程变化。
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公开(公告)号：US20240425973A1
公开(公告)日：2024-12-26
申请号：US18824461
申请日：2024-09-04
Applicant: VEECO INSTRUMENTS INC.
Inventor： Alexander I. Gurary , Mandar Deshpande , Ajit Paranjpe
Abstract: A method of cleaning wafer carriers includes the steps of: 1) loading a wafer carrier in need of cleaning into a cleaning chamber, injecting one or more cleaning gases into the cleaning chamber; 2) activating the one or more cleaning gases at a temperature ranging from about 400° C. to about 1000° C. under a pressure ranging from about 100 Torr to about 760 Torr; 3) exposing surfaces of the wafer carrier to the activated one or more cleaning gases; and 4) inspecting the wafer carrier surfaces using one or more surface characterization tools to determine if the wafer carrier has been cleaned.
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公开(公告)号：US20240175133A1
公开(公告)日：2024-05-30
申请号：US18519548
申请日：2023-11-27
Applicant: VEECO INSTRUMENTS INC.
Inventor： Ajit Paranjpe , Johannes Kaeppeler , Alexander Gurary
IPC: C23C16/458 , C23C16/455 , C30B25/10 , C30B25/12 , C30B25/14
CPC classification number: C23C16/4584 , C23C16/45502 , C23C16/45565 , C23C16/4586 , C30B25/10 , C30B25/12 , C30B25/14
Abstract: A multi-wafer metal organic chemical vapor deposition system in which adjacent wafers positioned within the system rotate about their own axes, including a reaction chamber comprising an exhaust system including a peripheral port, a multi-wafer carrier comprising a wafer carrier body and a plurality of wafer carrier discs supported within the wafer carrier body, wherein adjacent wafer carrier discs of the plurality wafer carrier discs are configured and the wafer carrier body are configured to rotate at different speeds, a multi-zone injection block positioned over the wafer carrier body, a central gas port positioned in the center of the wafer carrier body that can be configured as a gas exhaust or a gas injection port, and a multi-zone heater assembly positioned beneath the multi-wafer carrier.
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Patent Agency Ranking
公开(公告)号：US20160160387A1
公开(公告)日：2016-06-09
申请号：US14997180
申请日：2016-01-15
Applicant: Veeco Instruments Inc.
Inventor： William E. Quinn , Alexander Gurary , Ajit Paranjpe , Maria D. Ferreira , Roger P. Fremgen , Eric A. Armour
Abstract: A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers.
Abstract translation: 线性簇沉积系统包括以线性水平布置定位的多个反应室。 第一和第二反应气体歧管连接到每个反应室的相应工艺气体输入口。 具有多个排气输入的废气歧管与多个反应室中的每一个的废气输出端口连接。 基板输送车辆将基板和基板载体中的至少一个输送到每个反应室的基板输送口中并至少支撑至少一个基板。 选择每个反应室的工艺气体进入工艺气体输入口的流量和每个反应室中的压力中的至少一个，使得工艺条件在至少两个反应室中基本相同。
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公开(公告)号：US09356188B2
公开(公告)日：2016-05-31
申请号：US14480175
申请日：2014-09-08
Applicant: Veeco Instruments, Inc.
Inventor： Ajit Paranjpe , Jia Lee , Craig Metzner
CPC classification number: H01L33/0079 , H01L33/22
Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.
Abstract translation: 将应力层施加到半导体叠层，以便以预定深度分离半导体叠层。 将拉伸力施加到应力层上，在预定深度压裂半导体叠层，并允许半导体叠层的所得上部用于制造半导体最终产品（例如，发光二极管）。 所产生的半导体堆叠的下部可以重新用于在其上生长新的半导体叠层。
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公开(公告)号：US20150069420A1
公开(公告)日：2015-03-12
申请号：US14480175
申请日：2014-09-08
Applicant: Veeco Instruments, Inc.
Inventor： Ajit Paranjpe , Jia Lee , Craig Metzner
CPC classification number: H01L33/0079 , H01L33/22
Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.
Abstract translation: 将应力层施加到半导体叠层，以便以预定深度分离半导体叠层。 将拉伸力施加到应力层上，在预定深度压裂半导体叠层，并允许半导体叠层的所得上部用于制造半导体最终产品（例如，发光二极管）。 所产生的半导体堆叠的下部可以重新用于在其上生长新的半导体叠层。
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9.发明申请公开(公告)号：US20250109493A1
公开(公告)日：2025-04-03
申请号：US18899637
申请日：2024-09-27
Applicant: VEECO INSTRUMENTS INC.
Inventor： Johannes Kaeppeler , Ajit Paranjpe
IPC: C23C16/44 , C23C16/458
Abstract: A chemical vapor deposition system includes a reaction chamber and a removable wafer carrier including a wafer carrier body that is configured to support a wafer. The system includes a removable cover plate that supports the wafer carrier body and a susceptor base is disposed below the cover plate that supports the cover plate. The removable cover plate is in a nested arrangement with respect to the susceptor base as a result of first nesting structure of the removable cover plate mating with a second nesting structure of the susceptor base.
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公开(公告)号：US09978934B2
公开(公告)日：2018-05-22
申请号：US14927604
申请日：2015-10-30
Applicant: Veeco Instruments, Inc.
Inventor： Ajit Paranjpe , Boris Druz , Katrina Rook , Narasimhan Srinivasan
Abstract: This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.
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