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1.发明申请STRUCTURE OF CAPACITOR SET AND METHOD FOR REDUCING CAPACITANCE VARIATION BETWEEN CAPACITORS 有权电容器结构和减少电容之间电容变化的方法公开(公告)号：US20080012092A1
公开(公告)日：2008-01-17
申请号：US11309164
申请日：2006-07-04
申请人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L29/00
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译： 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。
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公开(公告)号：US08114752B2
公开(公告)日：2012-02-14
申请号：US12701521
申请日：2010-02-06
申请人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译： 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。
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公开(公告)号：US20100140741A1
公开(公告)日：2010-06-10
申请号：US12701521
申请日：2010-02-06
申请人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译： 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。
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公开(公告)号：US08133792B2
公开(公告)日：2012-03-13
申请号：US11309164
申请日：2006-07-04
申请人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译： 描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。 第一电容器包括并联电连接的多个第一电容器单元。 第二电容器包括并联电连接的多个第二电容器单元。 第一和第二电容器单元彼此空间上相互混合以形成阵列。
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5.发明申请CONDUCTIVE SHIELDING PATTERN AND SEMICONDUCTOR STRUCTURE WITH INDUCTOR DEVICE 审中-公开导电屏蔽图案和具有电感器器件的半导体结构公开(公告)号：US20080029854A1
公开(公告)日：2008-02-07
申请号：US11462269
申请日：2006-08-03
IPC分类号： H01L23/552
CPC分类号： H01L23/5227 , H01L23/5225 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to a conductive shielding pattern for shielding a inductor device. The conductive shielding pattern comprises a plurality of conductive layers and a plurality of diffusion regions. The conductive layers are located on a substrate. The diffusion regions are located in the substrate and the conductive layers and the diffusion regions are arranged alternatively and are free ends respectively.
摘要翻译： 本发明涉及用于屏蔽电感器件的导电屏蔽图案。 导电屏蔽图案包括多个导电层和多个扩散区域。 导电层位于基底上。 扩散区域位于衬底中，并且导电层和扩散区域交替排列并分别是自由端。
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6.发明授权Method for fabricating a transformer integrated with a semiconductor structure 有权用于制造与半导体结构集成的变压器的方法公开(公告)号：US07367113B2
公开(公告)日：2008-05-06
申请号：US11278952
申请日：2006-04-06
IPC分类号： H01F41/02
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译： 提供基板，并在其上形成顶部互连金属层和初级绕组层。 然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。 在钝化层上形成次级绕组层和至少一个焊盘。 接合焊盘通过通孔电连接到顶部互连金属层。
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公开(公告)号：US07321285B2
公开(公告)日：2008-01-22
申请号：US11736565
申请日：2007-04-17
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
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8.发明申请公开(公告)号：US20070236320A1
公开(公告)日：2007-10-11
申请号：US11736565
申请日：2007-04-17
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译： 提供基板，并在其上形成顶部互连金属层和初级绕组层。 然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。 在钝化层上形成次级绕组层和至少一个焊盘。 接合焊盘通过通孔电连接到顶部互连金属层。
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公开(公告)号：US20070234554A1
公开(公告)日：2007-10-11
申请号：US11278952
申请日：2006-04-06
IPC分类号： H01F7/06
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
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公开(公告)号：US07167072B2
公开(公告)日：2007-01-23
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译： 公开了一种在其上具有介电层的基板上形成的电感器。 电感器包括第一电感器图案，第二电感器图案，第三电感器图案。 第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案， 第二电感器图案和第三电感器图案具有相似的图案。 因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。
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