-
公开(公告)号：US20100065903A1
公开(公告)日：2010-03-18
申请号：US12284086
申请日：2008-09-18
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L47/00
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
摘要翻译： 在一个实施例中，垂直HVFET包括半导体材料的柱状半导体材料的柱，其布置成具有至少两个具有第一宽度的至少两个基本上平行且基本上线性的圆角部分的环形布局，以及至少两个圆形部分， 具有比第一宽度窄的第二宽度，第一导电类型的源极区域设置在柱的顶表面处或附近，并且第二导电类型的主体区域设置在源极区域下方的柱中。 第一和第二电介质区域分别设置在柱的相对侧上，第一介质区域被柱侧向包围，第二介质区域横向围绕柱。 第一和第二场板分别设置在第一和第二电介质区域中。
-
公开(公告)号：US08395207B2
公开(公告)日：2013-03-12
申请号：US13134504
申请日：2011-06-08
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L29/772
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
摘要翻译： 在一个实施例中，垂直HVFET包括半导体材料的柱状半导体材料的柱，其布置成具有至少两个具有第一宽度的至少两个基本上平行且基本上线性的圆角部分的环形布局，以及至少两个圆形部分， 具有比第一宽度窄的第二宽度，第一导电类型的源极区域设置在柱的顶表面处或附近，并且第二导电类型的主体区域设置在源极区域下方的柱中。 第一和第二电介质区域分别设置在柱的相对侧上，第一介质区域被柱侧向包围，第二介质区域横向围绕柱。 第一和第二场板分别设置在第一和第二电介质区域中。
-
公开(公告)号：US07964912B2
公开(公告)日：2011-06-21
申请号：US12284086
申请日：2008-09-18
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L29/772
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
摘要翻译： 在一个实施例中，垂直HVFET包括半导体材料的柱状半导体材料的柱，其布置成具有至少两个具有第一宽度的至少两个基本上平行且基本上线性的圆角部分的环形布局，以及至少两个圆形部分， 具有比第一宽度窄的第二宽度，第一导电类型的源极区域设置在柱的顶表面处或附近，并且第二导电类型的主体区域设置在源极区域下方的柱中。 第一和第二电介质区域分别设置在柱的相对侧上，第一介质区域被柱侧向包围，第二介质区域横向围绕柱。 第一和第二场板分别设置在第一和第二电介质区域中。
-
公开(公告)号：US20110233657A1
公开(公告)日：2011-09-29
申请号：US13134504
申请日：2011-06-08
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
-
公开(公告)号：US20120273885A1
公开(公告)日：2012-11-01
申请号：US13532583
申请日：2012-06-25
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译： 在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱 地区。 栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。 栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域 超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。
-
公开(公告)号：US20120146105A1
公开(公告)日：2012-06-14
申请号：US13385264
申请日：2012-02-10
IPC分类号： H01L27/06
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，在JFET的端子处提供的电压基本上与外部电压成比例 的JFET。 当外部电压大于夹断电压时，端子处提供的电压基本上恒定。 当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。 当外部电压为负时，电阻限制注入基板的电流。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。
-
公开(公告)号：US20120061755A1
公开(公告)日：2012-03-15
申请号：US13199792
申请日：2011-09-09
IPC分类号： H01L29/78
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译： 在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。 第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 邻接第一和第二部分的晶体管段的外场板被分离或部分合并。
-
公开(公告)号：US20110140166A1
公开(公告)日：2011-06-16
申请号：US12930626
申请日：2011-01-11
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
-
公开(公告)号：US20110042726A1
公开(公告)日：2011-02-24
申请号：US12583426
申请日：2009-08-20
IPC分类号： H01L29/80 , H01L27/105
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，JFET端子处的电压基本上与外部电压成比例 的JFET。 当外部电压大于夹断电压时，端子处提供的电压基本上恒定。 当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。 当外部电压为负时，电阻限制注入基板的电流。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。
-
公开(公告)号：US07859037B2
公开(公告)日：2010-12-28
申请号：US11707418
申请日：2007-02-16
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。 这些部分基本上跨越半导体管芯排列成行和列。 一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在 第二方向，第一方向基本上与第二方向正交。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。
-
-
-
-
-
-
-
-
-
搜索结果
82 条记录 (耗时 0.023 秒)
