公开(公告)号：US08222691B2

公开(公告)日：2012-07-17

申请号：US12583745

申请日：2009-08-25

申请人： Vijay Parthasarathy ,  Martin H. Manley

发明人： Vijay Parthasarathy ,  Martin H. Manley

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/77 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/13055 ,  H01L2924/19043

摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

摘要翻译： 在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。 栅极氧化物在圆形部分处基本上更厚。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

公开(公告)号：US20090315105A1

公开(公告)日：2009-12-24

申请号：US12583745

申请日：2009-08-25

申请人： Vijay Parthasarathy ,  Martin H. Manley

发明人： Vijay Parthasarathy ,  Martin H. Manley

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/77 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/13055 ,  H01L2924/19043

摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

摘要翻译： 在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。 栅极氧化物在圆形部分处基本上更厚。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

公开(公告)号：US5517453A

公开(公告)日：1996-05-14

申请号：US306454

申请日：1994-09-15

申请人： Robert J. Strain ,  Martin H. Manley

发明人： Robert J. Strain ,  Martin H. Manley

IPC分类号： G11C16/16 ,  G11C7/00

CPC分类号： G11C16/16

摘要： An electrically-erasable, electrically programmable read-only memory (EEPROM) with multiple erase modes identifies sections of memory cells that have not received a write operation subsequent to the most recent erase operation and inhibits erasure of the memory cells in such sections. An indicator column is formed from indicator memory cells added to each section. During a write operation in which a section is first erased and then programmed, the EEPROM reads the indicator memory cell added to the section and inhibits the erase of the section if the memory cells in the section are in an erased state.

摘要翻译： 具有多个擦除模式的电可擦除电可编程只读存储器（EEPROM）识别在最近擦除操作之后尚未接收到写入操作的存储器单元的区段，并且禁止擦除这些区段中的存储器单元。 指示器列由添加到每个部分的指示器存储单元形成。 在首先擦除部分然后编程的写入操作期间，EEPROM读取添加到该部分的指示存储器单元，并且如果该部分中的存储器单元处于擦除状态，则禁止该部分的擦除。

公开(公告)号：US5115288A

公开(公告)日：1992-05-19

申请号：US728823

申请日：1991-07-09

申请人： Martin H. Manley

发明人： Martin H. Manley

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L21/2815 ,  H01L29/7881 ,  Y10S257/90

摘要： The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.

摘要翻译： 本发明提供一种集成电路制造方法，其利用导电间隔物来限定分裂栅极存储单元中的串联选择晶体管的栅极长度。 由于可以使用现有的集成电路处理技术以高精度来控制间隔物的长度，消除了与现有技术的分离栅电池相关的未对准问题。

公开(公告)号：US4339715A

公开(公告)日：1982-07-13

申请号：US142971

申请日：1980-04-23

申请人： Greville G. Bloodworth ,  Martin H. Manley

发明人： Greville G. Bloodworth ,  Martin H. Manley

IPC分类号： G01R33/06 ,  G01R33/02 ,  H01L29/82

CPC分类号： G01R33/02

摘要： A carrier-domain magnetometer (20) incorporating compensation for changes in its domain rotation frequency/magnetic flux density characteristic due to changes in operating conditions, e.g. electric bias and/or ambient temperature conditions, and/or due to ageing, compensation being obtained by providing means (24 to 28) for monitoring the ratio (F-F.sub.o)/F.sub.o where F is the domain rotation frequency when both a magnetic field biassing the magnetometer onto the linear part of its frequency/flux characteristic and a magnetic field to be sensed are applied, and F.sub.o is the domain rotation frequency when the biassing field only is applied.

摘要翻译： 载波域磁强计（20），其包括由于操作条件变化而引起的其域旋转频率/磁通密度特性的变化的补偿。 和/或环境温度条件，和/或由于老化，通过提供用于监测比率（F-Fo）/ Fo的装置（24至28）获得补偿，其中F是当磁场 将磁力计偏置在其频率/磁通特性的线性部分上，并施加要感测的磁场，并且Fo是仅施加偏置场时的域旋转频率。

公开(公告)号：US08513719B2

公开(公告)日：2013-08-20

申请号：US13453134

申请日：2012-04-23

申请人： Sujit Banerjee ,  Martin H. Manley

发明人： Sujit Banerjee ,  Martin H. Manley

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.

摘要翻译： 半导体器件包括P型衬底中的N型阱区。 MOSFET的源极区域与包括MOSFET的漏极的阱区域的边界横向分离。 MOSFET的绝缘栅极从源极区域横向延伸至至少刚好超过阱区域的边界。 形成电容性反熔丝的第一板的多晶硅层与形成反熔丝的第二板的阱区的区域绝缘。 通过在第一和第二电容板两端施加足以破坏第二电介质层的至少一部分的电压来编程反熔丝，从而将多晶硅层电气短路到HVFET的漏极。

公开(公告)号：US08164125B2

公开(公告)日：2012-04-24

申请号：US12800096

申请日：2010-05-07

申请人： Sujit Banerjee ,  Martin H. Manley

发明人： Sujit Banerjee ,  Martin H. Manley

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.

摘要翻译： 半导体器件包括P型衬底中的N型阱区。 MOSFET的源极区域与包括MOSFET的漏极的阱区域的边界横向分离。 MOSFET的绝缘栅极从源极区域横向延伸至至少刚好超过阱区域的边界。 形成电容性反熔丝的第一板的多晶硅层与形成反熔丝的第二板的阱区的区域绝缘。 通过在第一和第二电容板两端施加足以破坏第二电介质层的至少一部分的电压来编程反熔丝，从而将多晶硅层电气短路到HVFET的漏极。

公开(公告)号：US20110272758A1

公开(公告)日：2011-11-10

申请号：US12800096

申请日：2010-05-07

申请人： Sujit Banerjee ,  Martin H. Manley

发明人： Sujit Banerjee ,  Martin H. Manley

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

摘要翻译： 半导体器件包括P型衬底中的N型阱区。 MOSFET的源极区域与阱区域的边界横向分离，阱区域包括MOSFET的漏极。 MOSFET的绝缘栅极从源极区域横向延伸至至少刚好超过阱区域的边界。 形成电容性反熔丝的第一板的多晶硅层与形成反熔丝的第二板的阱区的区域绝缘。 通过在第一和第二电容板两端施加足以破坏第二电介质层的至少一部分的电压来编程反熔丝，从而将多晶硅层电气短路到HVFET的漏极。 提供该摘要以允许搜索者或其他读者快速确定技术公开的主题。

公开(公告)号：US07595523B2

公开(公告)日：2009-09-29

申请号：US11707820

申请日：2007-02-16

申请人： Vijay Parthasarathy ,  Martin H. Manley

发明人： Vijay Parthasarathy ,  Martin H. Manley

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/77 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/13055 ,  H01L2924/19043

摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

摘要翻译： 在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。 栅极氧化物在圆形部分处基本上更厚。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

公开(公告)号：US5882998A

公开(公告)日：1999-03-16

申请号：US55018

申请日：1998-04-03

申请人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

发明人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC分类号： H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

摘要翻译： 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。