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1.发明申请SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL 有权具有嵌入式动态随机存取存储器扫描的移位寄存器公开(公告)号：US20090010077A1
公开(公告)日：2009-01-08
申请号：US11772592
申请日：2007-07-02
IPC分类号： G11C7/00
CPC分类号： G11C19/184 , G11C11/41 , G11C14/00 , G11C29/32 , G11C2029/3202
摘要： A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
摘要翻译： 混合移位寄存器锁存器，其使用用于系统操作的静态存储器单元和仅用于测试操作的动态存储器单元。 在阵列单元中设置L1存储元件和L2存储元件。 L1存储元件包括静态随机存取存储单元。 L1存储元件在阵列单元的系统和测试操作期间使用。 L2存储元件包括动态随机存取存储单元。 L2存储元件仅在阵列单元的测试操作期间使用。
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2.发明授权Shift register latch with embedded dynamic random access memory scan only cell 有权移位寄存器锁存器与嵌入式动态随机存取存储器扫描单元格公开(公告)号：US07474574B1
公开(公告)日：2009-01-06
申请号：US11772592
申请日：2007-07-02
IPC分类号： G11C7/00
CPC分类号： G11C19/184 , G11C11/41 , G11C14/00 , G11C29/32 , G11C2029/3202
摘要： A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
摘要翻译： 混合移位寄存器锁存器，其使用用于系统操作的静态存储器单元和仅用于测试操作的动态存储器单元。 在阵列单元中设置L1存储元件和L2存储元件。 L1存储元件包括静态随机存取存储单元。 L1存储元件在阵列单元的系统和测试操作期间使用。 L2存储元件包括动态随机存取存储单元。 L2存储元件仅在阵列单元的测试操作期间使用。
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3.发明授权Apparatus and method for speeding up access time of a large register file with wrap capability 有权用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法公开(公告)号：US07243209B2
公开(公告)日：2007-07-10
申请号：US11044449
申请日：2005-01-27
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译： 提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。 利用该装置和方法，从电路配置中消除了传统寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列， 需要包装能力。 这些附加的主多路复用器接收读地址和移位的读字线信号。 另一个主复用器接收读地址和未移位的读字线信号。 来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址 系统。
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4.发明申请公开(公告)号：US20090251974A1
公开(公告)日：2009-10-08
申请号：US12098764
申请日：2008-04-07
CPC分类号： G11C7/18 , G11C7/12 , G11C11/413 , G11C2207/2227
摘要： A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.
摘要翻译： 存储器电路包括全局读位线，全局读位线锁存器和多个子阵列，每个子阵列包括第一和第二本地读位线，第一和第二本地写位线以及第一和第二多个数组 分别与第一和第二本地读取位线以及第一和第二本地写入位线相互连接的存储器单元。 本地读位线与本地写位线分离。 本地多路复用块与第一和第二本地读位线互连，并且被配置为在断言SLEEP信号时对第一和第二本地读位线进行接地，并且选择性地将本地读位线互连到全局读位线 。 全局复用块与全局读位线互连，并且被配置为在断言SLEEP信号时将全局读位线保持在基本放电状态，并将全局读位线互连到全局读位线锁存器。 还包括所述类型的电路的设计结构。
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公开(公告)号：US20080279015A1
公开(公告)日：2008-11-13
申请号：US12180520
申请日：2008-07-26
IPC分类号： G11C7/10
CPC分类号： G06F9/30141
摘要： A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.
摘要翻译： 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。
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6.发明授权Method for providing multiple reads/writes using a 2read/2write register file array 有权使用2read / 2write寄存器文件阵列提供多次读/写的方法公开(公告)号：US07400548B2
公开(公告)日：2008-07-15
申请号：US11054276
申请日：2005-02-09
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供了使用2Read / 2Write寄存器文件读取多个连续条目并且仅写入一个读取地址和一个写入地址的多个连续条目。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 还提供了通过仅对一个地址进行4至16个解码来写入连续条目的机制。 此外，提供了一种用于使用起始读取字地址和基于起始读取字地址生成的两个读取字线从寄存器堆栈数据读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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7.发明授权Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array 有权使用2Read / 2Write寄存器文件阵列提供多次读/写的装置和方法公开(公告)号：US07663963B2
公开(公告)日：2010-02-16
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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公开(公告)号：US07443737B2
公开(公告)日：2008-10-28
申请号：US10798902
申请日：2004-03-11
IPC分类号： G11C7/10
CPC分类号： G06F9/30141
摘要： A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.
摘要翻译： 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。
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公开(公告)号：US07679973B2
公开(公告)日：2010-03-16
申请号：US12180520
申请日：2008-07-26
IPC分类号： G11C7/10
CPC分类号： G06F9/30141
摘要： A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.
摘要翻译： 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。
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10.发明授权公开(公告)号：US07668035B2
公开(公告)日：2010-02-23
申请号：US12098764
申请日：2008-04-07
IPC分类号： G11C5/14
CPC分类号： G11C7/18 , G11C7/12 , G11C11/413 , G11C2207/2227
摘要： A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.
摘要翻译： 存储器电路包括全局读位线，全局读位线锁存器和多个子阵列，每个子阵列包括第一和第二本地读位线，第一和第二本地写位线以及第一和第二多个数组 分别与第一和第二本地读取位线以及第一和第二本地写入位线相互连接的存储器单元。 本地读位线与本地写位线分离。 本地多路复用块与第一和第二本地读位线互连，并且被配置为在断言SLEEP信号时对第一和第二本地读位线进行接地，并且选择性地将本地读位线互连到全局读位线 。 全局复用块与全局读位线互连，并且被配置为在断言SLEEP信号时将全局读位线保持在基本放电状态，并将全局读位线互连到全局读位线锁存器。 还包括所述类型的电路的设计结构。
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