公开(公告)号：US4357685A

公开(公告)日：1982-11-02

申请号：US168562

申请日：1980-07-14

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Aldo Magrucci ,  Guido Torelli

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Aldo Magrucci ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/32 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L29/7885 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/32 ,  H01L27/115

摘要： A nonvolatile memory of the electrically alterable kind comprises an orthogonal array of cells each including a floating-gate IGFET and an enhancement IGFET in series. For the programming or the reading of a selected cell, lying at the intersection of a row and a column of the array, a common gate lead for all the enhancement IGFETs of the row and a common drain lead for all the enhancement IGFETs of the column are energized with voltage dependent on the desired kind of operation. To write a bit in a cell, its floating gate is progressively charged in a succession of steps separated by reading operations to check on the conduction threshold of the cell; the charging ends when that threshold reaches a predetermined storage level. To cancel a written bit, the floating gate is progressively discharged in a succession of steps again separated by reading operations; the discharging is terminated when the conduction threshold reaches a predetermined cancellation level. The width and/or the amplitude of a voltage pulse applied to an accessible gate of the floating-gate IGFET during the successive charging or discharging steps may be increased after each reading step in which the desired level is not attained.

摘要翻译： 电可变类型的非易失性存储器包括每个包括浮栅IGFET和增强IGFET串联的单元的正交阵列。 对于位于阵列的行和列的交叉点处的选定单元的编程或读取，用于该行的所有增强型IGFET的公共栅极引线和用于该列的所有增强型IGFET的公共漏极引线 根据所需的操作类型而被电压通电。 为了在单元中写入一位，其浮动栅逐步地通过读取操作分离的步骤进行充电，以检查单元的导通阈值; 当该阈值达到预定的存储水平时，充电结束。 为了取消写入位，浮动栅逐步地通过读取操作分开地逐步排出; 当导通阈值达到预定的取消水平时，放电终止。 在连续充电或放电步骤中施加到浮栅IGFET的可访问栅极的电压脉冲的宽度和/或幅度可以在其中未达到期望水平的每个读取步骤之后增加。