公开(公告)号：US6005411A

公开(公告)日：1999-12-21

申请号：US777296

申请日：1996-12-27

申请人： Vincenzo Daniele

发明人： Vincenzo Daniele

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/094

CPC分类号： H03K19/17708 ,  H03K19/1736

摘要： The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed. Preferably, the flash memory cells are Fowler-Nordheim Effect cells.

摘要翻译： 本发明是具有通过闪存类型的存储器单元电连接的基本模块的单片集成可编程器件，这些单元允许对基本模块的信号线之间的信号路径进行编程和重新编程。 优选地，闪存单元是Fowler-Nordheim Effect细胞。

公开(公告)号：US5949666A

公开(公告)日：1999-09-07

申请号：US32282

申请日：1998-02-26

申请人： Vincenzo Daniele ,  Alessandro Manstretta ,  Paolo Rolandi ,  Guido Torelli

发明人： Vincenzo Daniele ,  Alessandro Manstretta ,  Paolo Rolandi ,  Guido Torelli

IPC分类号： G05F1/46 ,  H03K4/02 ,  H02M1/12 ,  G05F1/40 ,  G05F7/64

CPC分类号： G05F1/465 ,  H03K4/023

摘要： A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.

摘要翻译： 一种楼梯自适应电压发生器电路，包括分别通过第一和第二开关连接在第一电压基准和输出运算放大器之间的第一电容器。 电容器的端子也分别通过第三和第四开关连接到第二参考电压。 与第五开关串联的第二电容器与第一电容器并联连接。

公开(公告)号：US4875020A

公开(公告)日：1989-10-17

申请号：US287299

申请日：1988-12-21

申请人： Vincenzo Daniele ,  Marco M. Monti ,  Michele Taliercio ,  Piero Capocelli

发明人： Vincenzo Daniele ,  Marco M. Monti ,  Michele Taliercio ,  Piero Capocelli

IPC分类号： H01L27/04 ,  G06J1/00 ,  H01L21/82 ,  H01L21/822 ,  H03G3/02 ,  H03G5/02

CPC分类号： G06J1/00

摘要： An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.

公开(公告)号：US5673221A

公开(公告)日：1997-09-30

申请号：US592939

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：US4839768A

公开(公告)日：1989-06-13

申请号：US113113

申请日：1987-10-27

申请人： Vincenzo Daniele ,  Mirella Benedetti

发明人： Vincenzo Daniele ,  Mirella Benedetti

IPC分类号： H05F3/02 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/73 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01L27/0251 ,  Y10S257/927

摘要： The influence of the resistance of the connection between a terminal of voltage limiting diodes against discharges of electrostatic nature which may hit a pad of an integrated circuit and a respective common potential node of the integrated circuit (supply or ground node) is unsuspectably critical. A resistance of just few ohms may depress the maximum tolerable discharge voltage by several thousands volts and the relationship between such two parameters is hyperbolic. Such a critical resistance may advantageously be reduced by utilizing more levels of metallization purposely connected in parallel and/or by "shifting" the protection diodes near the real (and not virtual) common potential node of the circuit or by utilizing "ring" metallizations over different levels for both the common potential nodes of the circuit.

摘要翻译： 电压限制二极管的端子与可能撞击集成电路的焊盘和集成电路（电源或接地节点）的相应公共电位节点的静电特性的连接的电阻的影响是无关紧要的。 只有几欧姆的电阻可能会使最大容许放电电压下降几千伏特，并且这两个参数之间的关系是双曲线的。 这种临界电阻可以有利地通过利用更多级别的金属化来有目的地并联连接和/或通过在电路的实际（而不是虚拟的）公共电位节点附近的“移位”保护二极管，或者通过利用“环”金属化 电路的共同电位节点的不同电平。

公开(公告)号：US4310571A

公开(公告)日：1982-01-12

申请号：US34204

申请日：1979-04-27

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

IPC分类号： H01C17/24 ,  H01L21/02 ,  H01L21/033 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01C17/06

CPC分类号： H01L28/20 ,  H01L21/033 ,  Y10T29/49082 ,  Y10T29/49099

摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.

摘要翻译： 预定电阻率的丝状元素，例如 通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对 化学物质如能够侵蚀电介质层的氢氟酸。 接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。 此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。 如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。 最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。

公开(公告)号：US4992680A

公开(公告)日：1991-02-12

申请号：US456782

申请日：1989-12-27

申请人： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

发明人： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177 ,  H03K23/54

CPC分类号： H03K19/1735 ,  H03K19/17708 ,  H03K23/542

摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multfunctional blocks.

公开(公告)号：US5838612A

公开(公告)日：1998-11-17

申请号：US869072

申请日：1997-06-04

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

摘要： Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

摘要翻译： 用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路 。 对该节点连接由反馈回路控制的当前复制电路。 这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。

公开(公告)号：US5729490A

公开(公告)日：1998-03-17

申请号：US690059

申请日：1996-07-31

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C11/56 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632 ,  G11C2211/5633

摘要： A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.

摘要翻译： 用于感测可以在多个m = 2n（n> = Z）个不同编程级别中采取一个编程电平的多级非易失性存储器单元的方法提供了在预定条件下偏置要感测的存储器单元，因此 存储器单元以具有m个不同单元电流值的离散集合的值吸收单元电流，每个单元电流值对应于所述编程电平之一。 感测方法还提供：同时将电池电流与规定数量的参考电流进行比较，所述规定数量的参考电流具有包括在所述离散的一组m个电池电流值的最小值和最大值之间的值，并且将所述离散的一组m个电池电流值 多个子单元电流子集，用于确定单元电流所属的单元电流值的子集; 对于单元电流所属的单元电流值的子集重复步骤（a），直到单元电流所属的单元电流值的子集仅包括一个单元电流值，该单元电流值是电流值 的待读取的存储单元。

公开(公告)号：US5701265A

公开(公告)日：1997-12-23

申请号：US593650

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632

摘要： A serial dichotomic method for sensing multiple-level non-volatile memory cells which can take one of m=2.sup.n (n>=2) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, and for: a) comparing the cell current with a reference current which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values, thus dividing said plurality of cell current values into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current belongs comprises only one cell current value, which is the value for the current of the memory cell to be sensed.

摘要翻译： 用于感测可以采用m = 2n（n> = 2）个不同编程级中的一个的多级非易失性存储器单元的串行二分法方法提供在预定条件下偏置待感测的存储器单元，使得存储器 电池以具有多个m个不同电池电流值的值吸收电池电流，并且用于：a）将电池电流与参考电流进行比较，所述参考电流具有包含在所述多个m的最小值和最大值之间的值 电池电流值，从而将所述多个电池电流值分成两个多个电池电流值，并确定电池电流所属的电池电流值的子数量; b）重复步骤a），直到单元电流所属的单元电流值的子多个仅包含一个单元电流值，该单元电流值是要感测的存储单元的电流的值。