公开(公告)号：US06389577B1

公开(公告)日：2002-05-14

申请号：US09276389

申请日：1999-03-25

申请人： Visweswara Rao Kodali ,  Johnny James LeBlanc ,  Kevin William McCauley ,  Salim Ahmed Shah

发明人： Visweswara Rao Kodali ,  Johnny James LeBlanc ,  Kevin William McCauley ,  Salim Ahmed Shah

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.

摘要翻译： 提供了一种方法和实现系统，其中针对电路设计中的每个元件的输入信号规范，元件内部延迟和输出负载在迭代处理引擎中被利用以客观地确定并为所设计的电路提供定时规则数据库。 示意图数据库网表通过测试模型转换器程序运行，以在测试模型设计电路的门级提供测试模型数据库。 这些数据由设计人员通过工作站GUI进行处理，结果应用于I / O设计测试功能。 I / O设计测试功能的结果包括列出输出组合的列表，这些输入组合是列出输出所需的。 GUI准备一系列刺激，以使用定时模拟器测试电路。 基于定时仿真器的输出响应，编译了各种输入和输出负载条件下的延迟关系。

公开(公告)号：US6058496A

公开(公告)日：2000-05-02

申请号：US955442

申请日：1997-10-21

申请人： Pamela Sue Gillis ,  Kevin William McCauley ,  Ronald J. Prilik ,  Donald Lawrence Wheater ,  Francis Woytowich, Jr.

发明人： Pamela Sue Gillis ,  Kevin William McCauley ,  Ronald J. Prilik ,  Donald Lawrence Wheater ,  Francis Woytowich, Jr.

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/317

摘要： A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

摘要翻译： 用于测试半导体芯片的方法和装置包括为半导体芯片提供公共输入/输出（I / O）或双向I / O焊盘。 I / O焊盘电耦合到片外驱动器（OCD）和芯片外接收器（OCR）。 OCD，I / O焊盘和OCR组合在通用输入/输出（CIO）或双向I / O配置中。 I / O焊盘由外部测试仪有效地断开，测试连接到开路焊盘的IO电路的性能参数。

公开(公告)号：US06728914B2

公开(公告)日：2004-04-27

申请号：US09745603

申请日：2000-12-22

申请人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

发明人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

IPC分类号： G01R3128

CPC分类号： G01R31/318385 ,  G01R31/31858

摘要： For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.

摘要翻译： 对于逻辑电路中的每个逻辑门，确定包含门的所有路径，并且通过其每个输入或启动SRL和每个输出或捕获SRL之间的长度对路径进行分类。 路径被分配单个阈值，然后根据它们相对于阈值的路径长度分类被分成两组，每组中的所有路径被视为单个路径。 然后使用标准LBIST工具模拟伪随机LBIST图案。 当与逻辑门相关联的故障由长度高于阈值的路径的捕获​​SRL检测到时，故障被视为测试并从故障列表中标记出来。 当在低于阈值的任何路径中检测到故障时，它不会被标记，并且故障的测试继续进行，直到测试模式为低于阈值的组的所有路径。 当组件的所有故障路径都低于阈值时，已经测试了单独确定的测试生成程序。 在生成的测试中，故障被迫通过超过阈值的最长路径传播。