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公开(公告)号：US06770939B2
公开(公告)日：2004-08-03
申请号：US10256116
申请日：2002-09-26
IPC分类号： H01L2976
CPC分类号： H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.
摘要翻译： 一种包括在从第一电平到第n电平的衬底上形成的n个电路电平的电路的装置，其中n大于1，并且n个电路电平中的每一个具有材料参数变化，其至少部分地由 热处理操作同时应用于n个电路级中的一个以上。 一种包括多个电路电平的电路的装置，所述多个电路电平中的每一个具有基本相似的材料参数。
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公开(公告)号：US06627530B2
公开(公告)日：2003-09-30
申请号：US09746204
申请日：2000-12-22
IPC分类号： H01L214763
CPC分类号： H01L27/0688 , H01L21/32135 , H01L21/8221 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure. In terms of patterning techniques, a desired edge angle is targeted by modifying, for example, the etch chemistry from one that is generally anisotropic to one that has a horizontal component to achieve an edge angle that is slightly re-entrant (i.e., having negative slope).
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公开(公告)号：US06624011B1
公开(公告)日：2003-09-23
申请号：US09639750
申请日：2000-08-14
IPC分类号： H01L2100
CPC分类号： H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Postponing at least some thermal processing operations, as multiple levels of a three dimensional circuit are formed.
摘要翻译： 当形成三维电路的多个级别时，推迟至少一些热处理操作。
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公开(公告)号：US07071565B2
公开(公告)日：2006-07-04
申请号：US10255884
申请日：2002-09-26
CPC分类号： H01L27/0688 , H01L21/32135 , H01L21/8221 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.
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公开(公告)号：US07245000B2
公开(公告)日：2007-07-17
申请号：US10681504
申请日：2003-10-07
IPC分类号： H01L27/103
CPC分类号： H01L27/1021
摘要： A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.
摘要翻译： 描述了单片三维存储器阵列。 存储器阵列包括第一组条带，包括第一端子; 第二组条带，包括第二端子; 第三组条带，包括第三端子; 具有至少一个具有稍微正斜率的侧壁的第一柱，所述柱设置在所述第一和第二组条之间并连接所述第一和第二组条，并且包括第一P掺杂硅区，第一N掺杂硅区和第一绝缘区; 具有至少一个具有稍微正斜率的侧壁的第二柱，所述柱设置在所述第二和第三组条之间并连接所述第二和第三组条，并包括第二P掺杂硅区，第二N掺杂硅区和第二绝缘区; 其中每个支柱基本上没有桁条。
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公开(公告)号：US07413945B2
公开(公告)日：2008-08-19
申请号：US10681507
申请日：2003-10-07
IPC分类号： H01L21/00
CPC分类号： H01L27/1021
摘要： A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.
摘要翻译： 提供一种形成有源器件的方法。 该方法包括在第一多个层上执行第一图案化操作。 该第一构图操作定义了有源器件的第一特征。 然后，可以对第一多个层中的至少一层进行第二图案化操作。 该第二构图操作定义了有源器件的第二特征。 重要的是，基本上背对背地执行第一和第二图案形成操作，从而确保有源装置能够精确地起作用。
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公开(公告)号：US06952043B2
公开(公告)日：2005-10-04
申请号：US10185507
申请日：2002-06-27
IPC分类号： H01L27/102 , H01L29/06 , H01L29/868
CPC分类号： H01L27/1021
摘要： A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.
摘要翻译： 提供一种形成有源器件的方法。 该方法包括在第一多个层上执行第一图案化操作。 该第一构图操作定义了有源器件的第一特征。 然后，可以对第一多个层中的至少一层进行第二图案化操作。 该第二构图操作定义了有源器件的第二特征。 重要的是，基本上背对背地执行第一和第二图案形成操作，从而确保有源装置能够精确地起作用。
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公开(公告)号：US06486065B2
公开(公告)日：2002-11-26
申请号：US09746469
申请日：2000-12-22
IPC分类号： H01L21461
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/101
摘要： The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features. The gap between the features is filled with the dielectric material which is softer than the masking layer with respect to a planarization
摘要翻译： 本发明是制造半导体阵列的方法。 根据本发明，形成了具有上表面的半导体层。 然后在半导体层上形成掩模层。 然后对掩模层进行图案化。 蚀刻半导体层与图案化掩模层对准以限定存储器阵列特征。 特征之间的间隙填充有相对于平坦化而比掩模层软的电介质材料
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公开(公告)号：US07816188B2
公开(公告)日：2010-10-19
申请号：US09918853
申请日：2001-07-30
IPC分类号： H01L21/00
CPC分类号： H01L27/11206 , C23C8/36 , H01L21/32105 , H01L23/5252 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer having a precise thickness and uniformity. The high density plasma oxidation process can be used to fabricate gate oxide layers, passivation layers and antifuse layers in semiconductor devices such as semiconductor memory devices and multi-level memory arrays.
摘要翻译： 提供了一种高密度等离子体氧化工艺，其中形成具有预定厚度的电介质膜。 提供等离子体氧化条件使得电介质膜的生长速度受到限制，以便产生具有精确厚度和均匀性的电介质层。 高密度等离子体氧化工艺可用于制造诸如半导体存储器件和多级存储器阵列的半导体器件中的栅极氧化物层，钝化层和反熔丝层。
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公开(公告)号：US06541312B2
公开(公告)日：2003-04-01
申请号：US09746083
申请日：2000-12-22
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material. In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material. An antifuse material is formed on the top semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor film is formed on the antifuse material.
摘要翻译： 本发明涉及新颖的反熔丝阵列及其制造方法。 根据本发明的实施例，阵列包括具有顶部半导体材料的多个第一间隔开的轨道堆叠。 填充电介质位于第一多个间隔开的轨道堆叠之间，其中填充电介质延伸到半导体材料的顶表面之上。 在第一多个间隔开的轨道堆叠的半导体材料的顶部上形成反熔丝材料。 在反熔丝材料上形成具有下半导体材料的第二多个间隔开的轨道堆叠。在本发明的第二实施例中，阵列包括具有顶部半导体材料的第一多个间隔开的轨道堆叠。 填充电介质位于第一多个间隔开的轨道堆叠之间，其中填充电介质凹陷在半导体材料的顶表面下方。 在第一多个间隔开的轨道堆叠的顶部半导体材料上形成反熔丝材料。 在反熔丝材料上形成具有下半导体膜的第二多个间隔开的轨道堆叠。
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