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    Process for depositing electrode with high effective work function
    1.
    发明授权
    Process for depositing electrode with high effective work function 有权
    具有高效功能的电极沉积工艺

    公开(公告)号：US09136180B2

    公开(公告)日：2015-09-15

    申请号：US13359385

    申请日：2012-01-26

    申请人： Vladimir Machkaoutsan ,  Jan Willem Maes ,  Qi Xie

    发明人： Vladimir Machkaoutsan ,  Jan Willem Maes ,  Qi Xie

    IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    摘要： According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.

    摘要翻译： 根据一些实施例，形成具有高有效功函数的电极。 电极可以是晶体管的栅极，并且可以通过沉积第一层导电材料，将第一层暴露于含氢气体，并将第二层导电材料沉积在高k栅极电介质上形成 第一层。 可以使用其中衬底不暴露于等离子体或等离子体产生的自由基的非等离子体工艺来沉积第一层。 第一层露出的含氢气体可以包括可以是含氢等离子体的一部分的被激发的氢物质，并且可以是含氢基团。 在沉积第二层之前，第一层也可能暴露于氧气。 在一些实施例中，栅极堆叠中的栅电极的功函数可以为约5eV或更高。

    PROCESS FOR DEPOSITING ELECTRODE WITH HIGH EFFECTIVE WORK FUNCTION
    2.
    发明申请
    PROCESS FOR DEPOSITING ELECTRODE WITH HIGH EFFECTIVE WORK FUNCTION 有权
    具有高效工作功能沉积电极的工艺

    公开(公告)号：US20120309181A1

    公开(公告)日：2012-12-06

    申请号：US13359385

    申请日：2012-01-26

    申请人： Vladimir Machkaoutsan ,  Jan Willem Maes ,  Qi Xie

    发明人： Vladimir Machkaoutsan ,  Jan Willem Maes ,  Qi Xie

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    摘要： According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.

    摘要翻译： 根据一些实施例，形成具有高有效功函数的电极。 电极可以是晶体管的栅极，并且可以通过沉积第一层导电材料，将第一层暴露于含氢气体，并将第二层导电材料沉积在高k栅极电介质上形成 第一层。 可以使用其中衬底不暴露于等离子体或等离子体产生的自由基的非等离子体工艺来沉积第一层。 第一层露出的含氢气体可以包括可以是含氢等离子体的一部分的被激发的氢物质，并且可以是含氢基团。 在沉积第二层之前，第一层也可能暴露于氧气。 在一些实施例中，栅极堆叠中的栅电极的功函数可以为约5eV或更高。

    Method for adjusting the threshold voltage of a gate stack of a PMOS device
    5.
    发明授权
    Method for adjusting the threshold voltage of a gate stack of a PMOS device 有权
    用于调整PMOS器件的栅极堆叠的阈值电压的方法

    公开(公告)号：US08399344B2

    公开(公告)日：2013-03-19

    申请号：US12898911

    申请日：2010-10-06

    申请人： Dieter Pierreux ,  Vladimir Machkaoutsan ,  Jan Willem Maes

    发明人： Dieter Pierreux ,  Vladimir Machkaoutsan ,  Jan Willem Maes

    IPC分类号： H01L21/28

    CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L29/517

    摘要： A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3.

    摘要翻译： 一种用于制造半导体器件的方法，包括栅极电介质和栅电极的栅极堆叠，所述方法包括在半导体衬底上形成具有第一电负性的金属氧化物或半金属氧化物的栅极介电层; 形成电介质VT调整层，电介质VT调整层是具有第二电负性的金属氧化物或半金属氧化物; 以及在所述栅极电介质层和所述VT调整层上形成栅电极; 其中所述栅极叠层的有效功函数通过调谐介电VT调整层的厚度和组成而被调谐到期望值，并且其中第二电负性值高于第一电负性值和Al 2 O 3的电负性。

    METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF A GATE STACK OF A PMOS DEVICE
    6.
    发明申请
    METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF A GATE STACK OF A PMOS DEVICE 有权
    调整PMOS器件门极电压的方法

    公开(公告)号：US20110081775A1

    公开(公告)日：2011-04-07

    申请号：US12898911

    申请日：2010-10-06

    申请人： Dieter Pierreux ,  Vladimir Machkaoutsan ,  Jan Willem Maes

    发明人： Dieter Pierreux ,  Vladimir Machkaoutsan ,  Jan Willem Maes

    IPC分类号： H01L21/28

    CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L29/517

    摘要： A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3

    摘要翻译： 一种用于制造半导体器件的方法，包括栅极电介质和栅电极的栅极堆叠，所述方法包括在半导体衬底上形成具有第一电负性的金属氧化物或半金属氧化物的栅极介电层; 形成电介质VT调整层，电介质VT调整层是具有第二电负性的金属氧化物或半金属氧化物; 以及在所述栅极电介质层和所述VT调整层上形成栅电极; 其中通过调谐介电VT调整层的厚度和组成将所述栅极叠层的有效功函数调谐到期望值，并且其中第二电负性值高于Al2O3的第一电负性值和电负性

    STABLE SILICIDE FILMS AND METHODS FOR MAKING THE SAME
    7.
    发明申请
    STABLE SILICIDE FILMS AND METHODS FOR MAKING THE SAME 有权
    稳定的硅胶膜及其制备方法

    公开(公告)号：US20080224317A1

    公开(公告)日：2008-09-18

    申请号：US12035373

    申请日：2008-02-21

    申请人： Vladimir Machkaoutsan ,  Ernst H.A. Granneman

    发明人： Vladimir Machkaoutsan ,  Ernst H.A. Granneman

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L21/28518

    摘要： Highly thermally stable metal silicides and methods utilizing the metal silicides in semiconductor processing are provided. The metal silicides are preferably nickel silicides formed by the reaction of nickel with substitutionally carbon-doped single crystalline silicon which has about 2 atomic % or more substitutional carbon. Unexpectedly, the metal silicides are stable to temperatures of about 900° C. and higher and their sheet resistances are substantially unaffected by exposure to high temperatures. The metal silicides are compatible with subsequent high temperature processing steps, including reflow anneals of BPSG.

    摘要翻译： 提供了高度热稳定的金属硅化物和在半导体加工中利用金属硅化物的方法。 金属硅化物优选通过镍与具有约2原子％或更多的取代碳的替代碳掺杂单晶硅的反应形成的硅化镍。 出乎意料地，金属硅化物在约900℃和更高的温度下是稳定的，并且它们的薄层电阻基本上不受暴露于高温的影响。 金属硅化物与随后的高温处理步骤兼容，包括BPSG的回流退火。

    THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY ARRAY
    8.
    发明申请
    THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY ARRAY 审中-公开

    公开(公告)号：US20200212041A1

    公开(公告)日：2020-07-02

    申请号：US16728492

    申请日：2019-12-27

    申请人： Vladimir Machkaoutsan ,  Richard J. Hill

    发明人： Vladimir Machkaoutsan ,  Richard J. Hill

    IPC分类号： H01L27/108 ,  G11C11/404 ,  G11C11/402

    摘要： Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.

    Stable silicide films and methods for making the same
    9.
    发明授权
    Stable silicide films and methods for making the same 有权
    稳定的硅化物薄膜及其制造方法

    公开(公告)号：US08367548B2

    公开(公告)日：2013-02-05

    申请号：US12035373

    申请日：2008-02-21

    申请人： Vladimir Machkaoutsan ,  Ernst H. A. Granneman

    发明人： Vladimir Machkaoutsan ,  Ernst H. A. Granneman

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518

    摘要： Highly thermally stable metal silicides and methods utilizing the metal silicides in semiconductor processing are provided. The metal silicides are preferably nickel silicides formed by the reaction of nickel with substitutionally carbon-doped single crystalline silicon which has about 2 atomic % or more substitutional carbon. Unexpectedly, the metal silicides are stable to temperatures of about 900° C. and higher and their sheet resistances are substantially unaffected by exposure to high temperatures. The metal silicides are compatible with subsequent high temperature processing steps, including reflow anneals of BPSG.

    摘要翻译： 提供了高度热稳定的金属硅化物和在半导体加工中利用金属硅化物的方法。 金属硅化物优选通过镍与具有约2原子％或更多的取代碳的替代碳掺杂单晶硅的反应形成的硅化镍。 出乎意料地，金属硅化物在约900℃和更高的温度下是稳定的，并且它们的薄层电阻基本上不受暴露于高温的影响。 金属硅化物与随后的高温处理步骤兼容，包括BPSG的回流退火。