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公开(公告)号:US20220229731A1
公开(公告)日:2022-07-21
申请号:US17340027
申请日:2021-06-06
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Yoseph Pinto , Rampraveen Somasundaram
Abstract: A storage system comprises a non-volatile memory configured to store boot code and a control circuit connected to the non-volatile memory. In response to a first request from a host to transmit the boot code, the storage system commences transmission of the boot code to the host at a first transmission speed. Before successfully completing the transmission of the boot code to the host at the first transmission speed, it is determined the boot code transmission has failed. Therefore, the host will issue a second request for the boot code. In response to the second request for the boot code, and recognizing that this is a fallback condition because the previous transmission of the boot code failed, the storage apparatus re-transmits the boot code to the host at a lower transmission speed than the first transmission speed.
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公开(公告)号:US11137932B2
公开(公告)日:2021-10-05
申请号:US16700501
申请日:2019-12-02
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Rotem Sela , Yoseph Pinto
Abstract: Technology for detecting a capability set of a removable integrated circuit card, such as a removable memory card, is disclosed. The removable integrated circuit card has one or more capability pads that indicate a capability set of the removable integrated circuit card. The physical condition may be a physical configuration of one or more capability pads, such as size or location of a capability pad. A host device is able to determine the capability set of the removable integrated circuit card based on the physical condition of the capability pads. The host device may determine the capability set without the card being powered on, without reading a register in the card, or without exchanging commands with the card.
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公开(公告)号:US11653463B2
公开(公告)日:2023-05-16
申请号:US16899972
申请日:2020-06-12
Applicant: Western Digital Technologies, Inc.
Inventor: Yoseph Pinto , Michael Lavrentiev
IPC: H05K5/02
CPC classification number: H05K5/026 , H05K5/0208 , H05K5/0247
Abstract: A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
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公开(公告)号:US11087195B2
公开(公告)日:2021-08-10
申请号:US16375529
申请日:2019-04-04
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: Yoseph Pinto , Shajith Musaliar Sirajudeen
IPC: G06K19/06 , G06K19/077
Abstract: Memory cards having a nano card form factor configured according to different card standards. The nano card have a pair of opposed surfaces having a length and width of a nano SIM card in which a first group of interface pads on one of the opposed surfaces configured to mate with contact pins of a host device card slot operating per a PCIe memory card standard and a second group of interface pads configured to mate with contact pins of a host device card slot operating per a second memory card standard different than the PCIe memory card standard. The nano cards have patterns of pads allowing for vertical and horizontal insertion to a host device card slot being backward compatible with legacy host device card slots.
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公开(公告)号:US11461260B2
公开(公告)日:2022-10-04
申请号:US17179953
申请日:2021-02-19
Applicant: Western Digital Technologies, Inc.
Inventor: Yoseph Pinto , Shiva K , Eldhose Peter , Rakesh Balakrishnan
Abstract: A memory card has a plurality of pads including a first set of pads located to connect with host contacts arranged in a first configuration for communication according to the micro Secure Digital (microSD) standard, a second set of pads located to connect with host contacts arranged in a second configuration for communication according to the Peripheral Component Interface express (PCIe) protocol, and a third set of pads located to connect with host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard. The plurality of pads includes one or more common pads that are common to the second set of pads and the third set of pads.
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公开(公告)号:US20200264990A1
公开(公告)日:2020-08-20
申请号:US16434365
申请日:2019-06-07
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: John Burke , Yoseph Pinto
Abstract: A memory card socket interconnector is disclosed including a pair of cavities configured to receive a pair of memory cards. The cavities include patterns of memory card interconnect pads. A second surface of the socket interconnector includes socket interconnect pads, distributed across the second surface of the socket interconnector, which are electrically coupled to the memory card interconnect pads. The memory card socket interconnector may further include electrically conductive balls provided between the memory card pads and the memory card interconnect pads in each cavity to enable good electrical contact between the memory card pads and the memory card interconnect pads.
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公开(公告)号:US20240428038A1
公开(公告)日:2024-12-26
申请号:US18227499
申请日:2023-07-28
Applicant: Western Digital Technologies, Inc.
Inventor: Yoseph Pinto
IPC: G06K19/077
Abstract: A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
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公开(公告)号:US20210368636A1
公开(公告)日:2021-11-25
申请号:US16899972
申请日:2020-06-12
Applicant: Western Digital Technologies, Inc.
Inventor: Yoseph Pinto , Michael Lavrentiev
IPC: H05K5/02
Abstract: A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
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公开(公告)号:US11023394B2
公开(公告)日:2021-06-01
申请号:US16434365
申请日:2019-06-07
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor: John Burke , Yoseph Pinto
Abstract: A memory card socket interconnector is disclosed including a pair of cavities configured to receive a pair of memory cards. The cavities include patterns of memory card interconnect pads. A second surface of the socket interconnector includes socket interconnect pads, distributed across the second surface of the socket interconnector, which are electrically coupled to the memory card interconnect pads. The memory card socket interconnector may further include electrically conductive balls provided between the memory card pads and the memory card interconnect pads in each cavity to enable good electrical contact between the memory card pads and the memory card interconnect pads.
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公开(公告)号:US20250139395A1
公开(公告)日:2025-05-01
申请号:US18545527
申请日:2023-12-19
Applicant: Western Digital Technologies, Inc.
Inventor: Yoseph Pinto , Jegathese Dhanachandra Prakash , Nandha Kumar Mohanraj , Satish Kammar
IPC: G06K13/08 , G06K19/077 , H05K1/11
Abstract: A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
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